library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top_receive is
PORT (
SD: in STD_LOGIC;
CLK_IN: in STD_LOGIC;
DATA_OUT: out STD_LOGIC_VECTOR(3 downto 0);
DATA_IN: in STD_LOGIC_VECTOR(3 downto 0)
);
end top_receive;
architecture Behavioral of top_receive is
signal SD_int: std_logic;
signal DATA_IN_int: std_logic_vector(3 downto 0);
begin
SD_int <= SD;
DATA_IN_int(3 downto 0) <= DATA_IN(3 downto 0);
DATA_OUT(3 downto 0) <= DATA_IN_int(3 downto 0);
end Behavioral;