Problem with ripple of the LDO output

[gdhp]

hi all

i am designing a Low drop out regulator. the structure composes a band gap , a

error opamp, a pass pmos, a feed back resistance strings. The obtive of it is to

use the vref(1.2v) to generate the 1.5v output.

In my designing , THE error opamp using the folded cascode has the following character:
1: the DC Gain=100db, GB=70M
2: phase margin is 40

the load current is about from 100u to 5mA.

from the simulation results, i found the variation of 1.5v output is large.

so can anyone tell me how to compress the ripple of the output? is the pahase margin too small?

thanks!

 

[scottieman]

Re: a problem of LDO

hi all

i am designing a Low drop out regulator. the structure composes a band gap , a

error opamp, a pass pmos, a feed back resistance strings. The obtive of it is to

use the vref(1.2v) to generate the 1.5v output.

In my designing , THE error opamp using the folded cascode has the following character:
1: the DC Gain=100db, GB=70M
2: phase margin is 40

the load current is about from 100u to 5mA.

from the simulation results, i found the variation of 1.5v output is large.

so can anyone tell me how to compress the ripple of the output? is the pahase margin too small?

thanks!

I would like to ask a question for verification before any suggestion

1) The 40degree phase margin is measured as a whole LDO or JUST the amplifier alone?

Scottie

 

[gdhp]

a problem of LDO

the phase margin is the whole LDO's. The output is the 1.5v output!

 

[sunking]

a problem of LDO

does the phase margin is under what out put

 

[scottieman]

Re: a problem of LDO

the phase margin is the whole LDO's. The output is the 1.5v output!

Then what kind of simulation you are doing?
and under what condition, you get a ripple at the output of the LDO?

If you just apply a ramp at the Vin of your LDO and get a ripple at the output, then your LDO should be unstable. It means that the method you used to plot the phase margin can not represent the turth.

Scottie

 

[mitgrace]

Re: a problem of LDO

Does your LDO structure using current buffer ?
BEcasue it will enhace your phase margin ..

If you don't do any compensation in your LDO ,
I think your LDO must be osscillation .


There are many method to do compensation ,
current buffer is one of mwthod , And you must check the light load (100uA) .
Usually this is worst case

 

[gdhp]

a problem of LDO

to scottieman
i add the pulse current at the output. in the simulation , the output of 1.5v is variation.

to mitgrace
i don't use the current buffer. you mean use the current mirror at the output of opamp? can you explain it indetail?

 

[scottieman]

Re: a problem of LDO

to scottieman
i add the pulse current at the output. in the simulation , the output of 1.5v is variation.

to mitgrace
i don't use the current buffer. you mean use the current mirror at the output of opamp? can you explain it indetail?

What is the paramemter of the current pulse you use
(e.g. from what current level to other level).. and when will your output oscillate
e.g. from 0A to 100mA or others condition

also.. what is your input voltage

Scottie

 

[tsanlee]

Re: a problem of LDO

hi all

i am designing a Low drop out regulator. the structure composes a band gap , a

error opamp, a pass pmos, a feed back resistance strings. The obtive of it is to

use the vref(1.2v) to generate the 1.5v output.

In my designing , THE error opamp using the folded cascode has the following character:
1: the DC Gain=100db, GB=70M
2: phase margin is 40

the load current is about from 100u to 5mA.

from the simulation results, i found the variation of 1.5v output is large.

so can anyone tell me how to compress the ripple of the output? is the pahase margin too small?

thanks!


You can check these item?
1.the variation of Bandgap
Make sure the variation come from bandgap or erroramp.
2."variation of output ",Do you mean Line regulation or load regulatoin?
3.DC gain is 10000 Gain*BW=70M BW=7K ?
The B.W is too poor.

 

[mitgrace]

Re: a problem of LDO

Dear gdhp :

Using current buffer , It is the between Opamp and Power MOS , It will enhace your phase margin in the totoal system . You can search the topic of LDO . This method is useful for LDO .

 

[amitbhaiji]

Re: a problem of LDO

is 40degree is the phase margin of the full LDO or opamp alone.
what is the min and mnax current variation.
If 40degree is the phase margin of the entire system then under what load(current)
you have simulated this and what is the phase margin in another case.
Is it possible for you to put the snap shot of the LDO output

 

[jerock_qin]

Re: a problem of LDO

I would like to ask a question for verification before any suggestion

1) The 40degree phase margin is measured as a whole LDO or JUST the amplifier alone?

 

[fantaci]

Re: a problem of LDO

hi all

i am designing a Low drop out regulator. the structure composes a band gap , a

error opamp, a pass pmos, a feed back resistance strings. The obtive of it is to

use the vref(1.2v) to generate the 1.5v output.

In my designing , THE error opamp using the folded cascode has the following character:
1: the DC Gain=100db, GB=70M
2: phase margin is 40

the load current is about from 100u to 5mA.

from the simulation results, i found the variation of 1.5v output is large.

so can anyone tell me how to compress the ripple of the output? is the pahase margin too small?

thanks!

Do you mean the overshoot? You`d better check your bandwidth and phase margin of the openloop to see if you could prove bandwidth or phase margin.

 

[rajath]

Re: a problem of LDO

Dear gdhp :

Using current buffer , It is the between Opamp and Power MOS , It will enhace your phase margin in the totoal system . You can search the topic of LDO . This method is useful for LDO .

Can you please suggest any material which explains this concept further? By a current buffer, do you simply mean a source follower stage?

 

[scottieman]

Re: a problem of LDO

Dear gdhp :

Using current buffer , It is the between Opamp and Power MOS , It will enhace your phase margin in the totoal system . You can search the topic of LDO . This method is useful for LDO .

Can you please suggest any material which explains this concept further? By a current buffer, do you simply mean a source follower stage?

Yes, a simple source follower is okay. However, the overdrive voltage (Vgs-Vth) of your power MOS will be affected, making either your power MOS cannot be fully turned on (if PMOS source follower) or your power MOS can not be turned off (if NMOS source follower).

By putting a buffer in between the power MOs and error-amplifier, you can virtually split your pole (originally formed by the Cgg of power MOS and Rout of error-amp) into two relative high frequency pole. Still, compensation is required to stabilize the LDO.

Scottie