Problem with random spikes in EPROM output of TTL circuit

[Singapura]

TTL Problems

I have a PCB which I am presently troubleshooting. The portion which I
encountered some strange phenomenon is depicted in the attached
diagram.

Here, a free running oscillator clocks a counter which drives the address
of an EPROM. The data output of the EPROM is then latched to drive the
input of a DAC which then outputs a 19.2KHz sine wave. Except for the
DAC which operates from +15Vdc and -15Vdc, the rest of the circuit is
basically TTL.

In the process of monitoring the signals of this circuit, I discovered that
most of the time, the EPROM data output does not produce TTL-level
data activities. Instead, random spikes of approximately 2V were seen
and these spikes were latched to the DAC, causing the DAC to output
nothing.

The question is, for a digital device such as an EPROM, how is it possible
that random spikes can be generated at its output when it is directly
driving a latch only? Occassionally, I do obtain the desired data activities
expected but once I power off and on again, the random spikes reappear
again. What could have caused it?

Can anyone who've experienced this before give me some help?

Thanks in advance.

 

[skydiverc]

Re: TTL Problems

without a detailed schematic I cant do jack.
Anyone else?

 

[flatulent]

Re: TTL Problems

This is a timing problem. First, you should have a latch between the counter and the EPROM. Then you should do a timing analysis and see if each of the latches is clocked a sufficiently long time after the data at the input is present.

 

[IanP]

Re: TTL Problems

From your drawing it is difficult to say when you latch the output from the EProm and what controls that operation..

Probably you don't need a latch between counter and EProm but what you need is a small delay from the oscillator (I assume that each clock pulse from the oscillator increases count on the counter) to latch the output from the EProm for the duration of the clock pulse.

 

[Singapura]

Re: TTL Problems

Attached is the portion of the circuit which I mentioned. The random spikes, which are non-TTL (approx 2V) appears at the EPROM data output.

Again, except for the DAC-08 which uses +15Vdc and -15Vdc, the rest uses Vcc for their supply.

This is a production design. It worked in the system, the card I'm troubleshooting has the problem I stated.

Your comments and insight are appreciated. Thanks.

 

[IanP]

Re: TTL Problems

Assuming the following:

Vpp is connected to Vcc
PGM is connected to Vcc
CLK2 is connected to QD(1)
and EProm programmed with a code ..

this circuit should work as the counters are changing their stages at the rising edge of the clock pulse and the latch at the falling edge.

What is the clock frequency (2.457MHz)?
That means ≈200ns of clock pulse duration and with slower types of EProms may mean (address to output delay time) problems ..

 

[chinara]

Re: TTL Problems

Yes, the clock may be too fast for an asyncronous ram. Please slow the clock, then try it again.