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Problem with parameterized interface in System Verilog

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er.akhilkumar

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I am getting following elaboration errors while using parameterized interfaces:

ncelab: *E,TYCMPAT (TB top): formal and actual do not have assignment compatible data types (expecting datatype compatible with 'virtual interface interface_name#(.Integer_type_parameter(64))' but found an incompatible 'interface_name#(.integer_type_parameter(32)) instance' instead).

Everything is working fine when I am passing value to parameter equal to the default value. But when value passed is different than the default value it shows above error.

Following is the interface code:

interface interface_name #(parameter int integer_type_parameter = 64) ();

port declarations...
..........................

endinterface : interface_name

Following is interface's instantiation in Testbench top:

module testbench_top();

parameter int integer_type_parameter = 32; // when value is 64 everything is working fine

interface_name #(.integer_type_parameter(integer_type_parameter)) object_name ();

endmodule


Can anyone please help me in solving this problem?

Thanx
 

Is interger_type_parameter defined somewhere else with different data type? Try using 'localparam' in testbench top instead of 'parameter' and see if it make any difference.
 

By using localparam errors are increased. If I declare some parameter as localparam its scope is within that module, so when I am passing its value to any other parameter, value is not propagated, it picks default value. Can you provide any other solution?

Actually problem is not because of the parameter declared in module as I also tried passing value to interface instead of parameter as following:

interface_name #(.integer_type_parameter(32)) object_name ();
 

ncelab: *E,TYCMPAT (TB top): formal and actual do not have assignment compatible data types (expecting datatype compatible with 'virtual interface interface_name#(.Integer_type_parameter(64))' but found an incompatible 'interface_name#(.integer_type_parameter(32)) instance' instead).Thanx

Based on your error log, it looks like there is a typo error. See how '.Integer_type_parameter(64))' has 'I' uppercase but '(.integer_type_parameter(32)' has 'i' lowercase.
 

morris_mano this is an example. At my end I have taken care of these things.
 

I don't have problems in this example (ius 10.2). Please, give more detailed description interface_name and testbench_top.
 

Poluekt, have you tried this kind of code? I am using Cadence software and the original code is:

interface mirror_if #(parameter int P_NUM_INT = 64) ();

port declarations...
..........................

endinterface : mirror_if



module tb_top();

mirror_if #(.P_NUM_INT(32)) xi_mirror (); //if I pass 64 here everything work fine as default value of P_NUM_INT is 64 at interface declaration

endmodule



Other code which I am using has no impact on above code. Can you help me?
 

No issues (cadence ius 8.2, 10.2).
 

I don't understand why it is happening, it should work. The original elaboration error reported by the tool is:

ncelab: *E,TYCMPAT (testbench top file path): formal and actual do not have assignment compatible data types (expecting datatype compatible with 'virtual interface mirror_if#(.P_NUM_INT(64))' but found an incompatible 'mirror_if#(.P_NUM_INT(32)) instance' instead).

- - - Updated - - -

nchelp ncelab TYCMPAT
nchelp: 09.20-s038: (c) Copyright 1995-2011 Cadence Design Systems, Inc.
ncelab/TYCMPAT =
The tool has detected a type error. The type error could be due to:
- mismatching data types between left hand side and right hand side expressions of an assignment,
- mismatching data types between formal and actual of a task or function call,
- mismatching data types between a port declaration and the expression connected to the port,
- illegal data type for an operand of an operator,
- illegal data type for a primary expression used in a specific construct.
For correcting this problem, you need to ensure that the data types are compatible
according to section 6.9 of P1800 standard or that the datatype of the object is legal in this
context (section 8 of P1800).
 

Do you use virtual interface mirror_if type (for/within functions/tasks) within tb_top?
 
Last edited:

One thing to note is you cannot create object for interface inside class. It has to be defined as virtual interface.

This is how I usually structure the interface. I have design_tb where I connect DUT with 'Program' block.

In design_tb,

mirror_if #(.P_NUM_INT(32)) xi_mirror ();

design dut(.mirror_design_if(xi_mirror));

and ,

design_program inst0(.mirror_program_if(xi_mirror));

Inside, design_program, you can have list of all the test and instantiate driver object or checker object. When instantiating class object, you pass the interface to the object like

// object creation
driver tests;
tests = new(mirror_program_if);

Inside driver class,

class driver;
virtual mirror_if mirror_driver_if;
 

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