Problem with Netlist simulation using Cadence NCVerilog

[mahesh4100]

ncsim: *f,interr: internal error

Hi,

I am new to EDA tools. I have encountered the following problem. I have a netlist generated by XILINX. While simulating this netlist without SDF file I am getting the fillowing error:

ncsim: *F,INTERR: INTERNAL ERROR
Observed simulation time : 100 NS + 150615038
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL: ncsim 05.82-p001
HOSTNAME: ib-cslnx8
OPERATING SYSTEM: Linux 2.4.21-40.ELsmp #1 SMP Thu Feb 2 22:22:39 EST 2006 i686
MESSAGE: System virtual memory limit exceeded (0x10b0/0xbffb2ca8)
-----------------------------------------------------------------
ncverilog: *E,SIMERR: Error during Simulation (status 255), exiting.


Anybody please help me regarding this.

Thanks in advance
Mahesh

 

[aji_vlsi]

netlist simulation

Your best bet is to contact CDN support.

Hi,



ncsim: *F,INTERR: INTERNAL ERROR
Observed simulation time : 100 NS + 150615038
-----------------------------------------------------------------


Thanks in advance
Mahesh

Given that the number of DELTAs is a LOT here (150615038) I would imagine a zero delay loop some where. Did you try wiht delay_mode_unit? Look in cdsdoc for this "delay_mode".

Good Luck
Ajeetha, CVC
www.noveldv.com

 

[mahesh4100]

ncsim system virtual memory limit exceeded

Hi Ajeetha,

Thanks for your suggestion. I tried running simulation with delay_mode_zero option with Cadence-NCVerilog tool. This could not solve my problem. Can you suggest something else??

Thanks
Mahesh

 

[aji_vlsi]

system virtual memory limit exceeded and cadence

Hi Ajeetha,

Thanks for your suggestion. I tried running simulation with delay_mode_zero option with Cadence-NCVerilog tool. This could not solve my problem. Can you suggest something else??

Thanks
Mahesh

I was suggesting delay_mode_unit, have you tried that? There is a detailed method of "divide and conquer" that I'm currently trying to write an article on. But it is no way close to be in a form that I can share here. The broad idea is to start from top level and eliminate one block at a time to see which block causes this. A quick example:


top.chip has say 4 module instances:

b1, b2, b3, b4

Can we narrow it down to one of them? (By making a dummy module for the same)? Once done, this is a recursive process to locate the culprit. What we at CVC are trying is to automate this process, will take a while. A good example such as what you are looking at will be great, but I'm not sure if you can share it - can you?

Ajeetha, CVC
www.noveldv.com

 

[mahesh4100]

simerr status 255

Hi Ajeetha,

I also tried running the simulation with delay_mode_unit option. This could not solve my problem. Coming to "divide and conquer" method that you have suggested, my netlist does not maintain heirarchy. So, I could not divide my netlist into modules to locate the culprit.

Thanks
Mahesh

 

[aji_vlsi]

netlist simulation

Hi Ajeetha,

I also tried running the simulation with delay_mode_unit option. This could not solve my problem. Coming to "divide and conquer" method that you have suggested, my netlist does not maintain heirarchy. So, I could not divide my netlist into modules to locate the culprit.

Thanks
Mahesh

So you've a flat netlist? Did you ever have a hier one? Did that simulate well?

Anyway coming to the current issue - I believe one of the crudest ways is to bring up NC in cmd line mode:

ncsim -tcl, run 100 ns; 
step
step... 

(May be you can automate it do multi-stepping as "mstep 10", I did this with a simple TCL for loop for VCS a while ago)

This would hopefully "oscillate" bet'n a set of nets and logic and with a tool like Verdi/Debussy you can try and understand the "logic" (Simvision can do that as well, but not sure how well it displays abstract cells).

This is a really long process and can be tiring, so good luck!

Do you have any behavioral model such as PLL or something here? If so, that may be the issue. Did you see the timescale reported? Is that upto your expectation?

All guesses, no pin point solution - as I have least information about your design/netlist.

Good Luck
Ajeetha, CVC
www.noveldv.com

 

[mahesh4100]

netlist from ncverilog

Hi Ajeetha,

Thanks for your suggestions. I will try making use of those options.

Thanks
Mahesh