I am designing WB lna fr freq rand 3.1 Gz to 10 ghz, m using ads fr simulation of schematic......i am getting proper frequecy response for S21 plot bt the gain is negative can ny1 tell wat is the problem..............immediate help is appreciated........
also can ny1 tell me hw to draw layout using ads
@tyassin, Abhishekabs.......i am attaching the schematic, s-parameters and noise figure graph with this post......plzz let me knw wat the changes to be made to get proper s-aprametes and noise figure
thts great dude atleast u r getting positive gain......i ws trying tht fr last afew days................can u please send me the schematic file.......or mail on ganesh634@gmail.com
Otherwise it look OK. Although you have to pay attention that some og the components are a series combination of external and internal transistor components.
Maybee the transistor models are not the same???? but CMOS is not my strong point.
Hi Tyassin,
I got gain of around 12.5 db over the intrested frequency range......i increased the value of resistor in the o/p stage bt the return loss is still of concern....
Added after 1 minutes:
can nyone plz tell me hw to measure iip3 for the wideband lna using ads
hey Tyassin that document was really of great help................thnxs a lot................... please help me regarding how to draw layout of the above ckt using ADS....