chemaphy
Junior Member level 2
Hello all,
I am now designing a SiGe HBT ECL XOR gate. When I simulate my XOR gate, I tend to get the high glitches (see picture) in the transcient simulation. Can anyone tell me how to reduce those high glitches. I greatly appreciate for your help.
Thanks,
chemaphy
I am now designing a SiGe HBT ECL XOR gate. When I simulate my XOR gate, I tend to get the high glitches (see picture) in the transcient simulation. Can anyone tell me how to reduce those high glitches. I greatly appreciate for your help.
Thanks,
chemaphy