Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Problem with my ECL XOR gate

Status
Not open for further replies.

chemaphy

Junior Member level 2
Joined
Oct 13, 2005
Messages
22
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
1,440
Hello all,

I am now designing a SiGe HBT ECL XOR gate. When I simulate my XOR gate, I tend to get the high glitches (see picture) in the transcient simulation. Can anyone tell me how to reduce those high glitches. I greatly appreciate for your help.

Thanks,
chemaphy
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top