# Problem with MPEG2 videodecoder and ASIC/FPGA gates

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#### TVMaster

##### Newbie level 6
mpeg decoder vhdl

I compiled the iDCT core with the Xilinx Webpack software and it didn't even fit into an 200 000 gate FPGA. OK, perhaps it was a little bit bad described but normally this couldn't be. Then I compiled an Z80 CPU and it took about 50 % of an 200 000 gate Spartan II. As ASIC it has about 8000 gates. This is 10 times so much as I have expected! Then I read the synthesis results of the Sparc CPU from Jiri Gaisler and it was the same with it. Also 10 times so much gates in an Virtex FPGA. Now I have realized that I can't compare ASIC gates with these "FPGA gates". The indications for these Xilinx FPGAs are idiotic! :evil:

So my MPEG videodecoder would never fit into an 300k gate FPGA. And now I have the problem that I don't know what I should do now. Perhaps the decoder would fit into a Virtex FPGA but they are so expensive and manufactoring an ASIC is also very expensive. Has anyone a hint for me?

#### rntsay

##### Member level 4
vhdl mpeg

you (re)discovered the conversion factor 1 asic "gate" = 8-10 fpga "gate";
there's nothing you can do about that. if your design has a lot of multipliers, you can get the newer fpga with built-in hardcoded multipliers;
this helps, but for random logic the situation is the same.

as far as silicon area, asic will always be a lot smaller and cheaper to make than fpga, but the manufacture cost is huge, so it only makes sense if you think you will sell a lot of chips (100,000+) and if you have a lot of money (at least a few hunder thousand us $). if you're trying to make some money out of your design, try to prefect it and validate it; you might be able to sell it as IP to a big company. mpeg-2 is also relatively old; a lot of companies have existing asics that can do it. something newer and less available is easier to sell. #### roli ##### Full Member level 5 mpeg2 vhdl Technical: Given the amount of Multipliers in an MPEG2 decoder, you should think of maybe increasing the Clock speed by a factor of 3 (120Mhz - if that is impossible maybe to 80Mhz) - and reusing Multipliers (thus reducing the Multipliers Gate area by a factor of 3, or 2 respectively). Also check if it is possible to reduce the bit word-length of a Multiplier input Arguments. Also - have you optimized your Multipliers - there's whole theory (Booth...etc...) about how to do it. Market: The above notes by 'rntsay' are correct. Moreover, the main market for MPEG2 HW decoder chips (at least nowadays) - are DVD Players - where companies like Zoran are making buckets of Bucks ($\$M) from.
Maybe an MPEG4 ASIC for next generation compression (DivX, etc) is a feasible market.
And, of course, the other main market, is a SW MPEG2 decoder, used mainly on PCs....

#### juripero

##### Member level 4
mpeg 2 decoder vhdl

FPGA is not a good candidate for MPEG2 decoder, not efficient, too expensive

#### juripero

##### Member level 4
fpga mpeg2

FPGA is not a good candidate for MPEG2 decoder, not efficient, too expensive

#### jokkoX

##### Newbie level 6
vhdl mpeg decoder

Whatch out for the new 'low cost' Virtex 2 devices (spartan 3?). They will probably have hardware multipliers available and will be somewhat bigger. You'll have to wait until they're commercially available though! I hope Q2-Q3 2003 :roll:

#### kunjalan

##### Member level 1
vhdl mpeg encoder

It is verification only to design MPEG2 decoder to use FPGA.
Verify function to use FPGA and actuality chip need method that embody using ASIC.

#### Zerox100

##### Full Member level 6
mpeg2 vhdl implementation

Hi TVMaster,