Problem with minimum density of a layer rule

[ee484]

Hi, all ...

In my process, there are rules for minimum density of a layer.
Metal layers' density can be taken cared of, I think. However, how can I take care of poly layer density, which is about 15%. What should I do? Should I place fake poly layer without connecting anything?? or what should I do? Should I make poly to poly capacitor between VDD and VSS???


What you do you guys do??

 

[CK815]

Re: Minimum density Rule

Hi,

usually, foundries provide special filling runsets withtheir design kits to meet minimum densities on metal and poly. Most of the time, it is a DRC Runset which creates floating dummy rectangles on each layer and saves it as a cell. Look for such a runset in your DK documentation or let us know which DK you are using.

Regards,

C

 

[em1cr0nix]

Re: Minimum density Rule

if u are still in block designing, u can ignore this density rules.
u may check this errors in the top level (IC level).

 

[leohart]

Minimum density Rule

hi,I have question about min density rule.My drc requires min density 30% for each metal and 15% for poly,but in my application,there is some big area without any poly and/or metal,such as big photodiode up to 500*500um^2 without any p or m on it, so what can I do to deal with the min density rule?It surly cannot pass the DRC.

Someone told me to waive the DRC error and live with it,it will just cause me some yield loss,and this is apcceptable in test chip.I'm not sure about this,is it simply some yield loss?
Will the foundry refuse my final data if they find this DRC errors in it?

 

[runom]

Re: Minimum density Rule

using poly to poly dummy capacitor between vdd and gnd is a good idea, thats serves the both, help to pass density rule check and also helps in case of noisy ground.

placing poly on metal connection is other way.

 

[locos]

Re: Minimum density Rule

In our company, we usually put dummy poly resistors and capacitors on areas that we possibly can. If verification of density check is done on block level, it should be ignored. Consideration of the density check should be done on the chip level. One reason why we have this is to have the chip more planar after fabrication.

 

[gafsos]

Re: Minimum density Rule

Hello,

calibre -tiling to generate dummies,


gafsos

 

[fixrouter4400]

Minimum density Rule

Add my 2 cent

With my experience in dealing with the density errors...I would highly recommend all layout engineers and the like to fix the density errors in block layout...

As what locos said it's all about planarization after fabrication...therefore if you didn't fix the density error in block level still you don't achieve high level of planarization in that particular area(block).

cheers!

 

[stuck_adc]

Re: Minimum density Rule

we can wave this error at block level, but we need to fix it at chip level.

to fix this kind of error, if its only related to poly.....then you can put dummy poly strips or blocks ( strips preferred as small devices are effected at time of fabrication if a large body is arround them) and connect them to either vdd or vss.
first try to fill all the empty spaces where ever possible, at the same time try to be as much uniform as you can while placing poly strips as this will have a big impact on the yield.

if min density error is related to both diffusion and poly...........then try to place dummy transistors with large lengths ( fingering can be used) and connect to appropriate powersupply. each terminal (s/d/g/b) either to vdd or vss.


why to fix min density errors...............
if any metal layer or poly or diffusion layer is not uniformly distributed in that case at the time of fabrication blank spaces will be present at places where these layers are not present and at time of etching if this blank space is large enough, then some etchant will accumulate at these places and will effect the reliability to a great extent. so we need to fix these errors as well.