Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Problem with MIG Tool pin assignment in Virtex6 and MT41J64M16xx-187E

Status
Not open for further replies.

Port Map

Advanced Member level 4
Full Member level 1
Joined
Aug 24, 2013
Messages
118
Helped
15
Reputation
30
Reaction score
14
Trophy points
1,298
Visit site
Activity points
2,089
Hello every one,
I'm trying to design a pin placing between V6 FPGA and a DDR3 SDRAM with the part MT41J64M16xx-187E.

first problem is that this is not supported on MIG Tool when I select Virtex6, But It's available with Spartan6.

then I copy the specification I saw in Spartan6 MIG GUI and use in in V6 MIG GUI and use "create custom part" from GUI to create a new part.

Steps pass OK and and generation ends, but I see this problems.

1)there is no selectable "Burst Length" to select in Memory Option Dialog.
2) there is No A13 and A14 pin location in generated UCF file.
3) in a new MIG GUI when I select "Fixed pin out method" and reuse the created UCF file,
first step of pin assignments passes successfully but the BuffIO selection has errors :
"Insufficient pins for BUFIO:0...."

more info:
1) I'm using this banks:
bank 36-> Address/control
bank 26-> Data
bank 34->system clock.
2) Virtex6 FPGA is XC6vLX130T-ff1156 -1
3) Data width = 16.
4) Data Mask Enabled.
5) Other thing are default
6) I selected MT41J64M16xx-187E from SP605 schematics.
7) error :
error.jpg
8) Burst length problem:
error2.jpg
9) MIG Version is 3.9
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top