osm3000
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Hi everyone,
I've this annoying problem in my Verilog code.
This my code
What I want is to simply OR 'LUNSTATUS6 ' signal with another value - depending on a flag - and assign this to 'TSM_R_B_N '.
In the waveform however, when 'LUNSTATUS6' changes to 0, 'TSM_R_B_N' doesn't make any change.
Can anyone give me a help?
I've this annoying problem in my Verilog code.
This my code
HTML:
always @(posedge REF_CLK or negedge all_reset)
begin
if (~all_reset)
TSM_R_B_N <= 1'b0;
else if (clr_r_b_n)
TSM_R_B_N <= ( (1'b0) && LUNSTATUS6 );
else if (set_r_b_n)
TSM_R_B_N <= ( (1'b1) && LUNSTATUS6 );
end
What I want is to simply OR 'LUNSTATUS6 ' signal with another value - depending on a flag - and assign this to 'TSM_R_B_N '.
In the waveform however, when 'LUNSTATUS6' changes to 0, 'TSM_R_B_N' doesn't make any change.
Can anyone give me a help?
Last edited: