Problem with large capacitance in Assura RC extraction

[suederb]

caps2d rcx

Hi,
I have problem in doing Assura RC extraction. When I finished layout
and did the RC extraction, I found there was a large capacitance between
input and output.
I thought that it might be some misunderstanding in setting the environment.

the schematic and layout are shown below.
Is there somebody can help me the solve the problem?

thanks~

Netlist
.GLOBAL AVDD AGND
*
.SUBCKT sch_trig IN OUT
*
*
* caps2d version: 9
*
*
* TRANSISTOR CARDS
*
*
MN1 net050 OUT AVDD AGND nch L=0.18U W=0.6U
+ AD=0.204P AS=0.204P PD=1.88U PS=1.88U
+ sb=3.4e-07 sa=3.4e-07 nrs=0.566667 nrd=0.566667 model="nch" fw=6e-07
MN0 net050 IN AGND AGND nch L=1U W=0.3U
+ AD=0.102P AS=0.102P PD=1.28U PS=1.28U
+ sb=3.4e-07 sa=3.4e-07 nrs=1.13333 nrd=1.13333 model="nch" fw=3e-07
MN16 OUT IN net050 AGND nch L=0.5U W=5U
+ AD=1.7P AS=1.7P PD=10.68U PS=10.68U
+ sb=3.4e-07 sa=3.4e-07 nrs=0.068 nrd=0.068 model="nch" fw=5e-06
MP0 net043 IN AVDD AVDD pch L=1U W=0.3U
+ AD=0.102P AS=0.102P PD=1.28U PS=1.28U
+ sb=3.4e-07 sa=3.4e-07 nrs=1.13333 nrd=1.13333 model="pch" fw=3e-07
MP1 AGND OUT net043 AVDD pch L=0.18U W=0.75U
+ AD=0.255P AS=0.255P PD=2.18U PS=2.18U
+ sb=3.4e-07 sa=3.4e-07 nrs=0.453333 nrd=0.453333 model="pch" fw=7.5e-07
MP13 OUT IN net043 AVDD pch L=0.5U W=3.5U
+ AD=1.19P AS=1.19P PD=7.68U PS=7.68U
+ sb=3.4e-07 sa=3.4e-07 nrs=0.0971429 nrd=0.0971429 model="pch" fw=3.5e-06
*
*
* CAPACITOR CARDS
*
*
C1 IN AVDD 2.352E-16
C2 OUT AVDD 2.334E-16
C3 net050 AVDD 4.504E-17
C4 net043 AVDD 1.131E-16
C5 IN OUT 1.505E-01
C6 IN net050 2.334E-16
C7 IN net043 2.015E-16
C8 OUT net050 3.280E-16
C9 OUT net043 2.733E-16
C10 AVDD AGND 1.804E-15
C11 IN AGND 5.417E-16
C12 OUT AGND 5.026E-16
C13 net050 AGND 1.235E-16
C14 net043 AGND 5.323E-17
*
*
.ENDS sch_trig
*

 

[srivatsan]

Assura RCX Problem

Check your p2lvsfile, you may need to redefine your blocking layer. I would ask my prof or someone who knows cadence there.

Srivats

 

[suederb]

Re: Assura RCX Problem

Thanks,
I have looked into p2lvs file.
This file defines the sheet resistance of Metal X.
It doesn't contain any information about blocking.

example
pro_layer=metal1 ext_layer=metal1 sheet_res=(0.0988,0.175)(0.0942,0.3739)(0.0917,0.6939)(0.0907,1.014);

besides, the process is TSMC .13um 1P8M CMOS.
Does there anybody encounter the same problem?