Problem with jtag cable for xilinx cpld

[koce]

xilinx cpld jtag

Hi everyone,
I want to download my design on xilinx XC9572-15PCG44 using JTAG cable and xilinx ISE software v_9.2i. The problem is that I can't read ID Code from device. Error is: "The idcode from the device does not match the idcode in the bsdl file"
read idcode is: 0000000000000000000000 and
expected idcode is: 00101001010100000100000010010011.
I don't know where is the problem: jtag cable, cpld, software or something else.
I attached schematic file of my jtag cable.
Does anyone can help me?

Bojan

 

[echo47]

db25 jtag pinout

I haven't tried Paul Goossens' design. The bad ID code 0000000000000000000000 suggests the JTAG interface electronics isn't working. Try using an oscilloscope to see if the TCK, TMS, and TDI signals are reaching your CPLD. Also see if TDO from the CPLD is reaching parallel port pin 13.

Possibly helpful, here is an official schematic of the Xilinx Parallel Cable III:
**broken link removed**

 

[banjo]

db25 pinout jtag

Hi,

The ID code is returned via the TDO line. This is an open-drain output and requires the pullup resistor, R8. Make sure the pullup resistor is there is properly connected, and is powered.

I would check the following:

1. Make sure VDD is around 3V. Since you are getting power from the target board via Pin 1 of the connector, I would jumper out D2. It is not needed.
2. Make sure you are using HC parts, not HCT parts. HCT parts require a 5V power supply.
3. Double check all your wiring. Especially the pinout to the JTAG header and then DB25. It is easy to count DB25 pins from the wrong end and get the connections wrong.
4. Take a look at: https://www.xilinx.com/support/programr/jtag_cable.pdf
This is a Xilinx schematic of the cable interface. The signals are labeled and the part values are slightly different. Make sure your DB25 pinout matches this one as this is what the software is trying to interface to.

 

[nsakan]

xilinx parallel cable iii pinout

Hi,

I had a similar problem with the parallel cable. The solution was so simple that I was amazed: I just shortened the length of the cables from board with the tri-state drivers (74HC125) to something like 10-15 cm. After that all was working well. The length of the cable from parallel port to the board is not so critical (I have some 2.5 m extension cable and all works well).

I hope that this helped You,
Nenad Sakan

 

[koce]

jtag xilinx cpld open drain

Hi everybody,
I want to report you that I achieved to make my JTAG cable for Xilinx cpld.
Thank you everybody for yours efforts to help me!

We should colaborate, shouldn't we!?

)
Bojan