Problem with inserting scan and DFFs

[ls000rhb]

insert scan problem

Before inserting scan chain,i use the command set_dont_use "sdff"to avoid the scan FFs used in the design.however,when inserting scan,because the command set_dont_use previously,the scan DFFs can not replace the DFFs .what should i do?
how to solve the problem?

 

[silencer3]

Re: insert scan problem

first synthesize the design with dont_use attribute on SDFF. Once u get the final synthesized netlsit meeting your constraints, go to a second pass. in that remove dont_use on SDFF, insert the scan. i think this will work.

But i prefer to use Mentor tools for scan insertion as they are more powerful. Or let the scan insertion done by back-end where the scan is inserted along with foundry test structures.

 

[luancao]

Re: insert scan problem

To make things simple you could remove the dont_use attribute to the "SDFF", the scan counterpart of the DFF.

Don't worry about in synthesis the scanable DFF will be used. If you set the area 0, the DFF will be used instead of its scanable counterpart. ( of course DFF is smaller ).

Then you could get your work done in a unified enviroment.

 

[ls000rhb]

insert scan problem

how to remove the dont_use attribute?what command is needed?thank ahead

 

[tarkyss]

insert scan problem

silencer3, i have a question, if let the scan insertion done by back-end, how can you know the timing is good, you still need to use dc verification, but if the timing is bad, you must resynthesis again, the work of back end is wasted?

 

[william_qiu]

Re: insert scan problem

how to remove the dont_use attribute?what command is needed?thank ahead

use command remove_attribute xxx dont_touch

 

[ken_ooi]

Re: insert scan problem

silencer3, i have a question, if let the scan insertion done by back-end, how can you know the timing is good, you still need to use dc verification, but if the timing is bad, you must resynthesis again, the work of back end is wasted?

For scan, it will run at slow freq, typically 10 - 20MHz.
Normally, we just need to take care of the hold violation.

 

[Bigdot]

insert scan problem

In layout, you can use reorder function to fix hold violation

 

[funzero]

Re: insert scan problem

In my opinion , you can use one step compile strategy.
insert DFT ( scan ) prototol such as scan port scan chain scan mode , dont scan
define scan clock ,
constraint your design.
and synthesis tool can do it ready for you.
sample commands : compile -scan ( IN DC );

 

[stocking]

insert scan problem

If you use DC, you may use the command :set_scan_element

 

[oxford]

insert scan problem

good topic and good answers, thanks alot.
BTW, how to use Mentor DFT in DC flow?

 

[anjali]

Re: insert scan problem

i prefer the method specified by luancao. i think its the simpler way to insert the scan flops

 

[sam31]

Re: insert scan problem

Hi,

I think funzero method is best for scan insertion
DC provides all commands to do this
when you use compile -scan command DC instantiate SDFF and put scan_in & test_se of all SDFF to '0'
then with insert_dft command DC make the scan data path according to scan
configuration. Configuration is specified before insert_dft or other commands
like drc_dft (check DFT design rules)