Problem with implementing resolution function to std_logic_vector in VHDL

[kodadimet]

Hello,

I am trying to implement a resolution function for std_logic_vector in VHDL... Synthesize is ok but behavioral simulation gives me errors...

I declared

signal a_temp : res_a STD_LOGIC_VECTOR (3 DOWNTO 0);

In my main code, i tried to assign different values to a_temp ('res_a' is resolution function). Then i defined a package with the function 'res_a' in it as follows:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package resolution_deneme is

type bit_4_array is array (natural range <>) of std_logic_vector(3 downto 0);

-- Declare functions and procedure

function res_a ( input_a : bit_4_array) return std_logic_vector;


end resolution_deneme;


package body resolution_deneme is


function res_a ( input_a : bit_4_array) return std_logic_vector is

variable a_temp : std_logic_vector(3 downto 0);

begin


-- do something


return a_temp;

end res_a;

end resolution_deneme;



As I said before synthesize is ok, but behavioral simulation gives me the following error:

Signal cannot be unconstrainedERROR:Simulator:777 - Static elaboration of top level VHDL design unit test in library work failed

And the error points the signal declaration line:

signal a_temp : res_a STD_LOGIC_VECTOR (3 DOWNTO 0);

What do you think the problem is? Did i make mistake in defining the resolution function?

Thank you
Mete

 

[TrickyDicky]

Resolution Function

First question - why are you trying to build a resolution function for a vector, or anything for that matter? What are you hoping to achieve? I dont understand how it can actually produce real hardware.

Secondly : AFAIK, you can only have a resolved sybtype, not a resolved signal. for example std_logic is a resolved version of std_ulogic.

subtype std_logic is resolved std_ulogic;

The only real world application of std_logic over std_ulogic is that it allows you to define tri-state buffers. Otherwise for what 99% of what people are doing they could std_ulogic.

Basically - in my opinion, unless you have a good reason for writing a resolution function - just dont.

 

[kodadimet]

Re: Resolution Function

Thank you for the answer,

Let's take the signal 'a_temp' as an address for data storage, and we want the different parts of the code access and change it (making sure that they don't access and change it at the same time). The synhesizer doesn't allow us to do that and give multiple driver errors... To solve the issue, i want to define a resolution function that will seperate different kinds of access that different parts of code make and so that the synhesizer allow me to access the same signal and change it from different parts of the code.

Could you suggest a solution?

Thank you
Mete

 

[TrickyDicky]

Resolution Function

Use a mux.