there is a conflict for the fxmux.
here is the MAP report of the design:
Release 6.2.03i Map G.31a
Xilinx Mapping Report File for Design 'DW_apb_uart'
Design Information
------------------
Command Line : D:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2v6000-bf957-4 -cm
area -pr b -k 4 -c 100 -tx off -o DW_apb_uart_map.ncd DW_apb_uart.ngd
DW_apb_uart.pcf
Target Device : x2v6000
Target Package : bf957
Target Speed : -4
Mapper Version : virtex2 -- $Revision: 1.16.8.1 $
Mapped Date : Fri Apr 01 16:58:00 2005
Design Summary
--------------
Number of errors: 1
Number of warnings: 40
Logic Utilization:
Number of Slice Flip Flops: 228 out of 67,584 1%
Number of 4 input LUTs: 672 out of 67,584 1%
Logic Distribution:
Number of occupied Slices: 447 out of 33,792 1%
Number of Slices containing only related logic: 447 out of 447 100%
Number of Slices containing unrelated logic: 0 out of 447 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 727 out of 67,584 1%
Number used as logic: 672
Number used as a route-thru: 55
Number of bonded IOBs: 126 out of 684 18%
IOB Flip Flops: 25
Number of GCLKs: 30 out of 16 187% (OVERMAPPED)
Total equivalent gate count for design: 6,284
Additional JTAG gate count for IOBs: 6,048
Peak Memory Usage: 181 MB
NOTES:
Related logic is defined as being logic that shares connectivity -
e.g. two LUTs are "related" if they share common inputs.
When assembling slices, Map gives priority to combine logic that
is related. Doing so results in the best timing performance.
Unrelated logic shares no connectivity. Map will only begin
packing unrelated logic into a slice once 99% of the slices are
occupied through related logic packing.
Note that once logic distribution reaches the 99% level through
related logic packing, this does not mean the device is completely
utilized. Unrelated logic packing will then begin, continuing until
all usable LUTs and FFs are occupied. Depending on your timing
budget, increased levels of unrelated logic packing may adversely
affect the overall timing performance of your design.
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts
Section 1 - Errors
------------------
ERROR
ack:18 - The design is too large for the given device and package.
Please check the Design Summary section to see which resource requirement for
your design exceeds the resources available in the device.
If the slice count exceeds device resources you might try to disable
register ordering (-r). Also if your design contains AREA_GROUPs, you may be
able to improve density by adding COMPRESSION to your AREA_GROUPs if you
haven't done so already.
NOTE: An NCD file will still be generated to allow you to examine the mapped
design. This file is intended for evaluation use only, and will not process
successfully through PAR.
This mapped NCD file can be used to evaluate how the design's logic has been
mapped into FPGA logic resources. It can also be used to analyze
preliminary, logic-level (pre-route) timing with one of the Xilinx static
timing analysis tools (TRCE or Timing Analyzer).
Section 2 - Warnings
--------------------
WARNING:LIT:177 - Clock buffer BUFGMUX symbol
"physical_group_U_DW_apb_uart_tx_n179/U14" (output
signal=U_DW_apb_uart_tx_n179) does not drive clock loads. Driving only
non-clock loads with a clock buffer will cause ALL of the dedicated clock
routing resources for this buffer to be wasted. Some of the non-clock loads
are (maximum of 5 listed):
Pin I3 of U_DW_apb_uart_tx_U275
Pin I3 of U_DW_apb_uart_tx_U283
Pin I0 of U13
Pin I1 of U_DW_apb_uart_tx_U327
Pin I0 of physical_group_U_DW_apb_uart_tx_n274/U30
WARNING:LIT:177 - Clock buffer BUFGMUX symbol
"physical_group_u_dw_apb_uart_tx_n193_rnm0/U15" (output
signal=u_dw_apb_uart_tx_n193_rnm0) does not drive clock loads. Driving only
non-clock loads with a clock buffer will cause ALL of the dedicated clock
routing resources for this buffer to be wasted. Some of the non-clock loads
are (maximum of 5 listed):
Pin I1 of U_DW_apb_uart_tx_U295
Pin I1 of U13
Pin I3 of U_DW_apb_uart_tx_U284
Pin I2 of U_DW_apb_uart_tx_U240/bound
Pin I1 of physical_group_U_DW_apb_uart_tx_n210/U_DW_apb_uart_tx_U272
WARNING:LIT:177 - Clock buffer BUFGMUX symbol
"physical_group_U_DW_apb_uart_tx_n209/U18" (output
signal=U_DW_apb_uart_tx_n209) does not drive clock loads. Driving only
non-clock loads with a clock buffer will cause ALL of the dedicated clock
routing resources for this buffer to be wasted. Some of the non-clock loads
are (maximum of 5 listed):
Pin I2 of U_DW_apb_uart_tx_U77
Pin I2 of U_DW_apb_uart_tx_U252
Pin I2 of U_DW_apb_uart_tx_U233/bound
Pin I0 of syn400/bound
Pin I1 of physical_group_U_DW_apb_uart_tx_n57/U_DW_apb_uart_tx_U250
WARNING:LIT:177 - Clock buffer BUFGMUX symbol "physical_group_reg_addr<2>/U2"
(output signal=reg_addr<2>) does not drive clock loads. Driving only
non-clock loads with a clock buffer will cause ALL of the dedicated clock
routing resources for this buffer to be wasted. Some of the non-clock loads
are (maximum of 5 listed):
Pin I1 of U_DW_apb_uart_regfile_U565
Pin I1 of U_DW_apb_uart_regfile_U569
Pin I1 of U_DW_apb_uart_regfile_U570
Pin I1 of U_DW_apb_uart_regfile_U601
Pin I3 of U_DW_apb_uart_regfile_U642
WARNING:LIT:178 - Clock buffer BUFGMUX symbol "physical_group_n136/U270" (output
signal=n136) does not drive clock loads. Driving only non-clock loads with a
clock buffer will cause ALL of the dedicated clock routing resources for this
buffer to be wasted. The non-clock loads are:
Pin I1 of U_DW_apb_uart_fifo_U_rx_fifo_U49
Pin I1 of U_DW_apb_uart_fifo_U_rx_fifo_U50
Pin I1 of U_DW_apb_uart_fifo_U_rx_fifo_U52
Pin I0 of
physical_group_U_DW_apb_uart_fifo_U_rx_fifo_U51/1.0/U_DW_apb_uart_fifo_U_rx_f
ifo_U51/bound
WARNING:LIT:177 - Clock buffer BUFGMUX symbol "physical_group_n137/U271" (output
signal=n137) does not drive clock loads. Driving only non-clock loads with a
clock buffer will cause ALL of the dedicated clock routing resources for this
buffer to be wasted. Some of the non-clock loads are (maximum of 5 listed):
Pin I2 of U_DW_apb_uart_fifo_U_tx_fifo_U79
Pin I2 of U178/bound
Pin I2 of U_DW_apb_uart_fifo_U_tx_fifo_U66/bound
Pin I1 of
physical_group_U_DW_apb_uart_fifo_U_tx_fifo_n4/U_DW_apb_uart_fifo_U_tx_fifo_U
10
Pin I2 of
physical_group_U_DW_apb_uart_fifo_U_tx_fifo_n4/U_DW_apb_uart_fifo_U_tx_fifo_U
66
WARNING:LIT:177 - Clock buffer BUFGMUX symbol "physical_group_n141/U275" (output
signal=n141) does not drive clock loads. Driving only non-clock loads with a
clock buffer will cause ALL of the dedicated clock routing resources for this
buffer to be wasted. Some of the non-clock loads are (maximum of 5 listed):
Pin I2 of U177
Pin I1 of
physical_group_U_DW_apb_uart_fifo_U_rx_fifo_n47/U_DW_apb_uart_fifo_U_rx_fifo_
U47
Pin I3 of
physical_group_U_DW_apb_uart_fifo_U_rx_fifo_n47/U_DW_apb_uart_fifo_U_rx_fifo_
U51
Pin I1 of
physical_group_U_DW_apb_uart_fifo_U_rx_fifo_U51/1.0/U_DW_apb_uart_fifo_U_rx_f
ifo_U51/bound
Pin I0 of physical_group_U_DW_apb_uart_fifo_U_rx_fifo_U51/1.0/U213
WARNING:LIT:178 - Clock buffer BUFGMUX symbol "physical_group_n152/U286" (output
signal=n152) does not drive clock loads. Driving only non-clock loads with a
clock buffer will cause ALL of the dedicated clock routing resources for this
buffer to be wasted. The non-clock loads are:
Pin I3 of U_DW_apb_uart_fifo_U_rx_fifo_U10
Pin I1 of U_DW_apb_uart_fifo_U_rx_fifo_syn250
Pin I3 of U_DW_apb_uart_fifo_U_rx_fifo_syn255
Pin I1 of U293
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol "physical_group_rx_ram_in_8_OBUF/U29" (output signal=rx_ram_in_8_OBUF)
has a mix of clock and non-clock loads. The non-clock loads are:
Pin D of U_DW_apb_uart_rx_rx_shift_reg_reg_8_
Pin I2 of U_DW_apb_uart_regfile_U398
Pin D of U_DW_apb_uart_regfile_rbr_ir_reg_8_
Pin I3 of U_DW_apb_uart_regfile_U587/free/bound
WARNING:LIT:177 - Clock buffer BUFGMUX symbol "physical_group_n29/U39" (output
signal=n29) does not drive clock loads. Driving only non-clock loads with a
clock buffer will cause ALL of the dedicated clock routing resources for this
buffer to be wasted. Some of the non-clock loads are (maximum of 5 listed):
Pin I2 of U_DW_apb_uart_regfile_U560
Pin S of U_DW_apb_uart_fifo_U_rx_fifo_U32
Pin I2 of U_DW_apb_uart_fifo_U_rx_fifo_U35
Pin S of U_DW_apb_uart_fifo_U_rx_fifo_U77
Pin I0 of physical_group_rx_ram_we_n_OBUF/U_DW_apb_uart_fifo_U_rx_fifo_U40
WARNING:LIT:178 - Clock buffer BUFGMUX symbol "physical_group_n34/U66" (output
signal=n34) does not drive clock loads. Driving only non-clock loads with a
clock buffer will cause ALL of the dedicated clock routing resources for this
buffer to be wasted. The non-clock loads are:
Pin I2 of U_DW_apb_uart_fifo_U_rx_fifo_U10
Pin I3 of U_DW_apb_uart_fifo_U_rx_fifo_syn250
Pin I2 of U_DW_apb_uart_fifo_U_rx_fifo_syn255
Pin I3 of U293
WARNING:LIT:177 - Clock buffer BUFGMUX symbol
"physical_group_U_DW_apb_uart_regfile_n212/U_DW_apb_biu_U14" (output
signal=U_DW_apb_uart_regfile_n212) does not drive clock loads. Driving only
non-clock loads with a clock buffer will cause ALL of the dedicated clock
routing resources for this buffer to be wasted. Some of the non-clock loads
are (maximum of 5 listed):
Pin I0 of U_DW_apb_uart_regfile_U579
Pin I1 of U_DW_apb_uart_regfile_U658
Pin I0 of U_DW_apb_uart_regfile_U704
Pin CE of U_DW_apb_biu_prdata_reg_0_
Pin CE of U_DW_apb_biu_prdata_reg_1_
WARNING:LIT:177 - Clock buffer BUFGMUX symbol
"physical_group_U_DW_apb_uart_fifo_tx_pop_n/U_DW_apb_uart_fifo_U45" (output
signal=U_DW_apb_uart_fifo_tx_pop_n) does not drive clock loads. Driving only
non-clock loads with a clock buffer will cause ALL of the dedicated clock
routing resources for this buffer to be wasted. Some of the non-clock loads
are (maximum of 5 listed):
Pin S of U_DW_apb_uart_fifo_U_tx_fifo_U33
Pin I2 of U_DW_apb_uart_fifo_U_tx_fifo_U45
Pin I1 of U_DW_apb_uart_fifo_U_tx_fifo_U79
Pin I1 of U178/bound
Pin I0 of
physical_group_U_DW_apb_uart_fifo_U_tx_fifo_n4/U_DW_apb_uart_fifo_U_tx_fifo_U
8
WARNING:LIT:177 - Clock buffer BUFGMUX symbol
"physical_group_U_DW_apb_uart_fifo_rx_push_n/U_DW_apb_uart_fifo_U47" (output
signal=U_DW_apb_uart_fifo_rx_push_n) does not drive clock loads. Driving only
non-clock loads with a clock buffer will cause ALL of the dedicated clock
routing resources for this buffer to be wasted. Some of the non-clock loads
are (maximum of 5 listed):
Pin I3 of U_DW_apb_uart_regfile_U664
Pin I0 of U_DW_apb_uart_fifo_U_rx_fifo_U10
Pin I0 of U_DW_apb_uart_fifo_U_rx_fifo_net9412
Pin I1 of U_DW_apb_uart_fifo_U_rx_fifo_syn151
Pin I2 of U_DW_apb_uart_fifo_U_rx_fifo_syn250
WARNING:LIT:178 - Clock buffer BUFGMUX symbol
"physical_group_U_DW_apb_uart_fifo_U_rx_fifo_n8/U_DW_apb_uart_fifo_U_rx_fifo_
U14" (output signal=U_DW_apb_uart_fifo_U_rx_fifo_n8) does not drive clock
loads. Driving only non-clock loads with a clock buffer will cause ALL of the
dedicated clock routing resources for this buffer to be wasted. The non-clock
loads are:
Pin I3 of U_DW_apb_uart_fifo_U_rx_fifo_syn252
Pin I0 of U63
Pin I2 of U169
Pin I1 of U282
WARNING:LIT:178 - Clock buffer BUFGMUX symbol
"physical_group_U_DW_apb_uart_fifo_U_rx_fifo_n4/U_DW_apb_uart_fifo_U_rx_fifo_
U9" (output signal=U_DW_apb_uart_fifo_U_rx_fifo_n4) does not drive clock
loads. Driving only non-clock loads with a clock buffer will cause ALL of the
dedicated clock routing resources for this buffer to be wasted. The non-clock
loads are:
Pin I1 of U_DW_apb_uart_fifo_U_rx_fifo_net9408
Pin I0 of U_DW_apb_uart_fifo_U_rx_fifo_U44
Pin I3 of U63
Pin I2 of U282
WARNING:LIT:178 - Clock buffer BUFGMUX symbol
"physical_group_U_DW_apb_uart_fifo_U_tx_fifo_n13/U_DW_apb_uart_fifo_U_tx_fifo
_U21" (output signal=U_DW_apb_uart_fifo_U_tx_fifo_n13) does not drive clock
loads. Driving only non-clock loads with a clock buffer will cause ALL of the
dedicated clock routing resources for this buffer to be wasted. The non-clock
loads are:
Pin I1 of
physical_group_U_DW_apb_uart_fifo_U_tx_fifo_n30/U_DW_apb_uart_fifo_U_tx_fifo_
syn273
Pin I1 of physical_group_U_DW_apb_uart_fifo_U_tx_fifo_n30/U76/bound
Pin I1 of
physical_group_U_DW_apb_uart_fifo_U_tx_fifo_n30/U_DW_apb_uart_fifo_U_tx_fifo_
syn269
Pin I2 of
physical_group_U_DW_apb_uart_fifo_U_tx_fifo_net3893/U_DW_apb_uart_fifo_U_tx_f
ifo_syn300
Pin I2 of physical_group_U_DW_apb_uart_fifo_U_tx_fifo_net3893/U69/bound
WARNING:LIT:177 - Clock buffer BUFGMUX symbol
"physical_group_to_det_cnt_ens<1>/U_DW_apb_uart_regfile_U535" (output
signal=to_det_cnt_ens<1>) does not drive clock loads. Driving only non-clock
loads with a clock buffer will cause ALL of the dedicated clock routing
resources for this buffer to be wasted. Some of the non-clock loads are
(maximum of 5 listed):
Pin I2 of U_DW_apb_uart_fifo_U42
Pin D of U_DW_apb_uart_regfile_dly_fen_reg
Pin S of U_DW_apb_uart_regfile_U550
Pin S of U_DW_apb_uart_regfile_U551
Pin S of U_DW_apb_uart_regfile_U552
WARNING:LIT:178 - Clock buffer BUFGMUX symbol
"physical_group_U_DW_apb_uart_regfile_n437/U_DW_apb_uart_regfile_U544"
(output signal=U_DW_apb_uart_regfile_n437) does not drive clock loads.
Driving only non-clock loads with a clock buffer will cause ALL of the
dedicated clock routing resources for this buffer to be wasted. The non-clock
loads are:
Pin I2 of U_DW_apb_uart_regfile_U538
Pin I2 of U_DW_apb_uart_regfile_U600
Pin I2 of U_DW_apb_uart_regfile_U641
Pin I2 of U220
Pin I1 of U_DW_apb_uart_regfile_U671/free/bound
WARNING:LIT:178 - Clock buffer BUFGMUX symbol
"physical_group_U_DW_apb_uart_regfile_n438/U_DW_apb_uart_regfile_U545"
(output signal=U_DW_apb_uart_regfile_n438) does not drive clock loads.
Driving only non-clock loads with a clock buffer will cause ALL of the
dedicated clock routing resources for this buffer to be wasted. The non-clock
loads are:
Pin I3 of U_DW_apb_uart_regfile_U538
Pin S of U_DW_apb_uart_regfile_U601
Pin I0 of U_DW_apb_uart_regfile_U642
Pin I3 of U220
Pin I3 of U_DW_apb_uart_regfile_U671/free/bound
WARNING:LIT:177 - Clock buffer BUFGMUX symbol
"physical_group_U_DW_apb_uart_regfile_n439/U_DW_apb_uart_regfile_U546"
(output signal=U_DW_apb_uart_regfile_n439) does not drive clock loads.
Driving only non-clock loads with a clock buffer will cause ALL of the
dedicated clock routing resources for this buffer to be wasted. Some of the
non-clock loads are (maximum of 5 listed):
Pin I0 of U_DW_apb_uart_regfile_U538
Pin I0 of U_DW_apb_uart_regfile_U602
Pin I0 of U_DW_apb_uart_regfile_U604
Pin I3 of U_DW_apb_uart_regfile_U641
Pin I1 of U_DW_apb_uart_regfile_U671
WARNING:LIT:178 - Clock buffer BUFGMUX symbol
"physical_group_U_DW_apb_uart_regfile_n440/U_DW_apb_uart_regfile_U547"
(output signal=U_DW_apb_uart_regfile_n440) does not drive clock loads.
Driving only non-clock loads with a clock buffer will cause ALL of the
dedicated clock routing resources for this buffer to be wasted. The non-clock
loads are:
Pin I1 of U_DW_apb_uart_regfile_U538
Pin S of U_DW_apb_uart_regfile_U603
Pin I2 of U_DW_apb_uart_regfile_U642
Pin I1 of U220
Pin I2 of U_DW_apb_uart_regfile_U671/free/bound
WARNING:LIT:177 - Clock buffer BUFGMUX symbol
"physical_group_tx_start/U_DW_apb_uart_regfile_U743" (output signal=tx_start)
does not drive clock loads. Driving only non-clock loads with a clock buffer
will cause ALL of the dedicated clock routing resources for this buffer to be
wasted. Some of the non-clock loads are (maximum of 5 listed):
Pin I1 of U_DW_apb_uart_tx_U116
Pin I3 of U_DW_apb_uart_tx_U117
Pin I3 of U_DW_apb_uart_tx_U120
Pin I3 of U_DW_apb_uart_tx_U123
Pin I3 of U_DW_apb_uart_tx_U126
WARNING:LIT:178 - Clock buffer BUFGMUX symbol
"physical_group_U_DW_apb_uart_regfile_n558/U_DW_apb_uart_regfile_U745"
(output signal=U_DW_apb_uart_regfile_n558) does not drive clock loads.
Driving only non-clock loads with a clock buffer will cause ALL of the
dedicated clock routing resources for this buffer to be wasted. The non-clock
loads are:
Pin I1 of U_DW_apb_uart_regfile_U579
Pin I1 of U234
WARNING:LIT:177 - Clock buffer BUFGMUX symbol
"physical_group_U_DW_apb_uart_regfile_n559/U_DW_apb_uart_regfile_U746"
(output signal=U_DW_apb_uart_regfile_n559) does not drive clock loads.
Driving only non-clock loads with a clock buffer will cause ALL of the
dedicated clock routing resources for this buffer to be wasted. Some of the
non-clock loads are (maximum of 5 listed):
Pin I1 of U_DW_apb_uart_to_det_U79
Pin D of U_DW_apb_uart_regfile_dly_rx_pop_reg
Pin I0 of U_DW_apb_uart_regfile_U664
Pin I2 of U121
Pin I1 of physical_group_U_DW_apb_uart_regfile_n219/U179
WARNING:LIT:177 - Clock buffer BUFGMUX symbol
"physical_group_U_DW_apb_uart_regfile_n570/U_DW_apb_uart_regfile_U757"
(output signal=U_DW_apb_uart_regfile_n570) does not drive clock loads.
Driving only non-clock loads with a clock buffer will cause ALL of the
dedicated clock routing resources for this buffer to be wasted. Some of the
non-clock loads are (maximum of 5 listed):
Pin CE of U_DW_apb_uart_regfile_rbr_ir_reg_0_
Pin CE of U_DW_apb_uart_regfile_rbr_ir_reg_1_
Pin CE of U_DW_apb_uart_regfile_rbr_ir_reg_2_
Pin CE of U_DW_apb_uart_regfile_rbr_ir_reg_3_
Pin CE of U_DW_apb_uart_regfile_rbr_ir_reg_4_
WARNING:LIT:178 - Clock buffer BUFGMUX symbol
"physical_group_rx_finish/U_DW_apb_uart_rx_U264" (output signal=rx_finish)
does not drive clock loads. Driving only non-clock loads with a clock buffer
will cause ALL of the dedicated clock routing resources for this buffer to be
wasted. The non-clock loads are:
Pin S of U11
Pin CE of U_DW_apb_uart_rx_rx_shift_reg_reg_9_
Pin S of U_DW_apb_uart_rx_U185
Pin D of U_DW_apb_uart_regfile_rx_push_en_ed_reg
Pin I0 of U_DW_apb_uart_regfile_U707
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol "physical_group_rx_ram_in_9_OBUF/U_DW_apb_uart_rx_U265" (output
signal=rx_ram_in_9_OBUF) has a mix of clock and non-clock loads. The
non-clock loads are:
Pin I3 of U_DW_apb_uart_regfile_U398
Pin D of U_DW_apb_uart_regfile_rbr_ir_reg_9_
Pin I2 of U_DW_apb_uart_regfile_U587/free/bound
WARNING:LIT:177 - Clock buffer BUFGMUX symbol
"physical_group_final_rx_in/U_DW_apb_uart_rx_U266" (output
signal=final_rx_in) does not drive clock loads. Driving only non-clock loads
with a clock buffer will cause ALL of the dedicated clock routing resources
for this buffer to be wasted. Some of the non-clock loads are (maximum of 5
listed):
Pin I0 of syn457
Pin D of U_DW_apb_uart_to_det_dly_final_rx_in_reg
Pin I3 of U_DW_apb_uart_to_det_U79
Pin D of U_DW_apb_uart_rx_rx_shift_reg_reg_9_
Pin I1 of U_DW_apb_uart_rx_U188
WARNING:LIT:177 - Clock buffer BUFGMUX symbol
"physical_group_U_DW_apb_uart_tx_n189/U_DW_apb_uart_tx_U222" (output
signal=U_DW_apb_uart_tx_n189) does not drive clock loads. Driving only
non-clock loads with a clock buffer will cause ALL of the dedicated clock
routing resources for this buffer to be wasted. Some of the non-clock loads
are (maximum of 5 listed):
Pin I2 of U_DW_apb_uart_tx_U283
Pin I0 of syn396
Pin I0 of U_DW_apb_uart_tx_U327
Pin I3 of U_DW_apb_uart_tx_U234/bound
Pin I3 of U_DW_apb_uart_tx_U240/free/bound
WARNING
ack:266 - The function generator U_DW_apb_uart_regfile_U652 failed to
merge with F5 multiplexer U_DW_apb_uart_regfile_U644. There is more than one
MUXF5. The design will exhibit suboptimal timing.
WARNING
ack:266 - The function generator U_DW_apb_uart_regfile_U711 failed to
merge with F5 multiplexer U_DW_apb_uart_regfile_U644. There is a conflict
for the FXMUX. The design will exhibit suboptimal timing.
WARNING
ack:266 - The function generator U_DW_apb_uart_fifo_U_rx_fifo_U39
failed to merge with F5 multiplexer U_DW_apb_uart_fifo_U_rx_fifo_U32. There
is a conflict for the FXMUX. The design will exhibit suboptimal timing.
WARNING
ack:266 - The function generator U_DW_apb_uart_fifo_U_rx_fifo_U39
failed to merge with F5 multiplexer U_DW_apb_uart_fifo_U_rx_fifo_U77. There
is a conflict for the FXMUX. The design will exhibit suboptimal timing.
WARNING
ack:266 - The function generator syn713 failed to merge with F5
multiplexer U11. There is a conflict for the FXMUX. The design will exhibit
suboptimal timing.
WARNING
ack:266 - The function generator net13324 failed to merge with F5
multiplexer U21. There is a conflict for the FXMUX. The design will exhibit
suboptimal timing.
WARNING
ack:266 - The function generator U_DW_apb_uart_bclk_gen_U43 failed to
merge with F5 multiplexer U95. There is a conflict for the FXMUX. The
design will exhibit suboptimal timing.
WARNING
ack:266 - The function generator U_DW_apb_uart_rx_U233 failed to merge
with F5 multiplexer U_DW_apb_uart_rx_U223. There is a conflict for the
FXMUX. The design will exhibit suboptimal timing.
WARNING
ack:266 - The function generator syn494 failed to merge with F5
multiplexer syn719. There is more than one MUXF5. The design will exhibit
suboptimal timing.
WARNING
ack:266 - The function generator net13324 failed to merge with F5
multiplexer syn719. There is a conflict for the FXMUX. The design will
exhibit suboptimal timing.
Section 3 - Informational
-------------------------
INFO:LIT:95 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic.
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
BUFG symbol "U14" (output signal=U_DW_apb_uart_tx_n179),
BUFG symbol "U15" (output signal=u_dw_apb_uart_tx_n193_rnm0),
BUFG symbol "U18" (output signal=U_DW_apb_uart_tx_n209),
BUFG symbol "U2" (output signal=reg_addr<2>),
BUFG symbol "U270" (output signal=n136),
BUFG symbol "U271" (output signal=n137),
BUFG symbol "U275" (output signal=n141),
BUFG symbol "U286" (output signal=n152),
BUFG symbol "U29" (output signal=rx_ram_in_8_OBUF),
BUFG symbol "U39" (output signal=n29),
BUFG symbol "U66" (output signal=n34),
BUFG symbol "U_DW_apb_biu_U14" (output signal=U_DW_apb_uart_regfile_n212),
BUFG symbol "U_DW_apb_uart_fifo_U45" (output
signal=U_DW_apb_uart_fifo_tx_pop_n),
BUFG symbol "U_DW_apb_uart_fifo_U47" (output
signal=U_DW_apb_uart_fifo_rx_push_n),
BUFG symbol "U_DW_apb_uart_fifo_U_rx_fifo_U14" (output
signal=U_DW_apb_uart_fifo_U_rx_fifo_n8),
BUFG symbol "U_DW_apb_uart_fifo_U_rx_fifo_U9" (output
signal=U_DW_apb_uart_fifo_U_rx_fifo_n4),
BUFG symbol "U_DW_apb_uart_fifo_U_tx_fifo_U21" (output
signal=U_DW_apb_uart_fifo_U_tx_fifo_n13),
BUFG symbol "U_DW_apb_uart_regfile_U535" (output signal=to_det_cnt_ens<1>),
BUFG symbol "U_DW_apb_uart_regfile_U544" (output
signal=U_DW_apb_uart_regfile_n437),
BUFG symbol "U_DW_apb_uart_regfile_U545" (output
signal=U_DW_apb_uart_regfile_n438),
BUFG symbol "U_DW_apb_uart_regfile_U546" (output
signal=U_DW_apb_uart_regfile_n439),
BUFG symbol "U_DW_apb_uart_regfile_U547" (output
signal=U_DW_apb_uart_regfile_n440),
BUFG symbol "U_DW_apb_uart_regfile_U743" (output signal=tx_start),
BUFG symbol "U_DW_apb_uart_regfile_U745" (output
signal=U_DW_apb_uart_regfile_n558),
BUFG symbol "U_DW_apb_uart_regfile_U746" (output
signal=U_DW_apb_uart_regfile_n559),
BUFG symbol "U_DW_apb_uart_regfile_U757" (output
signal=U_DW_apb_uart_regfile_n570),
BUFG symbol "U_DW_apb_uart_rx_U264" (output signal=rx_finish),
BUFG symbol "U_DW_apb_uart_rx_U265" (output signal=rx_ram_in_9_OBUF),
BUFG symbol "U_DW_apb_uart_rx_U266" (output signal=final_rx_in),
BUFG symbol "U_DW_apb_uart_tx_U222" (output signal=U_DW_apb_uart_tx_n189)
Section 4 - Removed Logic Summary
---------------------------------
1 block(s) removed
26 block(s) optimized away
2 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic reported below is either:
1. part of a cycle
2. part of disabled logic
3. a side-effect of other trimmed logic
The signal "U_DW_apb_uart_tx_n255" is unused and has been removed.
Unused block "U_DW_apb_uart_tx_U305" (BUF) removed.
The signal "n_Logic0_" is unused and has been removed.
Optimized Block(s):
TYPE BLOCK
GND U43
FDCE U_DW_apb_biu_prdata_reg_10_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_11_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_12_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_13_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_14_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_15_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_16_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_17_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_18_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_19_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_20_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_21_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_22_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_23_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_24_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_25_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_26_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_27_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_28_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_29_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_30_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_31_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_8_
optimized to 0
FDCE U_DW_apb_biu_prdata_reg_9_
optimized to 0
FDCE U_DW_apb_uart_tx_sir_break_ext_reg
optimized to 0
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Strength | Rate | | | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| baudout_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| cts_n | IOB | INPUT | LVTTL | | | INFF1 | | IFD |
| dcd_n | IOB | INPUT | LVTTL | | | INFF1 | | IFD |
| dma_rx_req_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| dma_tx_req_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| dsr_n | IOB | INPUT | LVTTL | | | INFF1 | | IFD |
| dtr_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| intr | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | |
| out1_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| out2_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| paddr<2> | IOB | INPUT | LVTTL | | | | | |
| paddr<3> | IOB | INPUT | LVTTL | | | | | |
| paddr<4> | IOB | INPUT | LVTTL | | | | | |
| paddr<5> | IOB | INPUT | LVTTL | | | | | |
| paddr<6> | IOB | INPUT | LVTTL | | | | | |
| paddr<7> | IOB | INPUT | LVTTL | | | | | |
| pclk | IOB | INPUT | LVTTL | | | | | |
| penable | IOB | INPUT | LVTTL | | | | | |
| prdata<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | |
| prdata<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | |
| prdata<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | |
| prdata<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | |
| prdata<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | |
| prdata<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | |
| prdata<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | |
| prdata<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | |
| prdata<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<10> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<11> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<16> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<17> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<18> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<19> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<20> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<21> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<22> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<23> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<24> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<25> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<26> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<27> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<28> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<29> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<30> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| prdata<31> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| presetn | IOB | INPUT | LVTTL | | | | | |
| psel | IOB | INPUT | LVTTL | | | | | |
| pwdata<0> | IOB | INPUT | LVTTL | | | INFF1 | | IFD |
| pwdata<1> | IOB | INPUT | LVTTL | | | INFF1 | | IFD |
| pwdata<2> | IOB | INPUT | LVTTL | | | INFF1 | | IFD |
| pwdata<3> | IOB | INPUT | LVTTL | | | INFF1 | | IFD |
| pwdata<4> | IOB | INPUT | LVTTL | | | INFF1 | | IFD |
| pwdata<5> | IOB | INPUT | LVTTL | | | INFF1 | | IFD |
| pwdata<6> | IOB | INPUT | LVTTL | | | INFF1 | | IFD |
| pwdata<7> | IOB | INPUT | LVTTL | | | INFF1 | | IFD |
| pwrite | IOB | INPUT | LVTTL | | | | | |
| ri_n | IOB | INPUT | LVTTL | | | INFF1 | | IFD |
| rts_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_in<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_in<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_in<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_in<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_in<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_in<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_in<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_in<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_in<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_in<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_out<0> | IOB | INPUT | LVTTL | | | | | |
| rx_ram_out<1> | IOB | INPUT | LVTTL | | | | | |
| rx_ram_out<2> | IOB | INPUT | LVTTL | | | | | |
| rx_ram_out<3> | IOB | INPUT | LVTTL | | | | | |
| rx_ram_out<4> | IOB | INPUT | LVTTL | | | | | |
| rx_ram_out<5> | IOB | INPUT | LVTTL | | | | | |
| rx_ram_out<6> | IOB | INPUT | LVTTL | | | | | |
| rx_ram_out<7> | IOB | INPUT | LVTTL | | | | | |
| rx_ram_out<8> | IOB | INPUT | LVTTL | | | | | |
| rx_ram_out<9> | IOB | INPUT | LVTTL | | | | | |
| rx_ram_rd_addr<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_rd_addr<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_rd_addr<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_rd_addr<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_rd_ce_n | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | |
| rx_ram_re_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_we_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_wr_addr<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_wr_addr<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_wr_addr<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rx_ram_wr_addr<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| rxrdy_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| scan_mode | IOB | INPUT | LVTTL | | | | | |
| sin | IOB | INPUT | LVTTL | | | INFF1 | | IFD |
| sout | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | |
| tx_ram_in<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_in<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_in<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_in<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_in<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_in<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_in<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_in<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_out<0> | IOB | INPUT | LVTTL | | | | | |
| tx_ram_out<1> | IOB | INPUT | LVTTL | | | | | |
| tx_ram_out<2> | IOB | INPUT | LVTTL | | | | | |
| tx_ram_out<3> | IOB | INPUT | LVTTL | | | | | |
| tx_ram_out<4> | IOB | INPUT | LVTTL | | | | | |
| tx_ram_out<5> | IOB | INPUT | LVTTL | | | | | |
| tx_ram_out<6> | IOB | INPUT | LVTTL | | | | | |
| tx_ram_out<7> | IOB | INPUT | LVTTL | | | | | |
| tx_ram_rd_addr<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_rd_addr<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_rd_addr<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_rd_addr<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_rd_ce_n | IOB | OUTPUT | LVTTL | 12 | SLOW | OFF1 | | |
| tx_ram_re_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_we_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_wr_addr<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_wr_addr<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_wr_addr<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| tx_ram_wr_addr<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
| txrdy_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |
+------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.
Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.
Section 11 - Timing Report
--------------------------
This design was not run using timing mode.
Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 13 - Additional Device Resource Counts
----------------------------------------------
Number of JTAG Gates for IOBs = 126
Number of Equivalent Gates for Design = 6,284
Number of RPM Macros = 0
Number of Hard Macros = 0
CAPTUREs = 0
BSCANs = 0
STARTUPs = 0
PCILOGICs = 0
DCMs = 0
GCLKs = 30
ICAPs = 0
18X18 Multipliers = 0
Block RAMs = 0
TBUFs = 0
Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 103
IOB Dual-Rate Flops not driven by LUTs = 0
IOB Dual-Rate Flops = 0
IOB Slave Pads = 0
IOB Master Pads = 0
IOB Latches not driven by LUTs = 0
IOB Latches = 0
IOB Flip Flops not driven by LUTs = 13
IOB Flip Flops = 25
Unbonded IOBs = 0
Bonded IOBs = 126
Total Shift Registers = 0
Static Shift Registers = 0
Dynamic Shift Registers = 0
16x1 ROMs = 0
16x1 RAMs = 0
32x1 RAMs = 0
Dual Port RAMs = 0
MUXFs = 46
MULT_ANDs = 0
4 input LUTs used as Route-Thrus = 55
4 input LUTs = 672
Slice Latches not driven by LUTs = 0
Slice Latches = 0
Slice Flip Flops not driven by LUTs = 90
Slice Flip Flops = 228
Slices = 447
Number of LUT signals with 4 loads = 16
Number of LUT signals with 3 loads = 32
Number of LUT signals with 2 loads = 110
Number of LUT signals with 1 load = 456
NGM Average fanout of LUT = 1.97
NGM Maximum fanout of LUT = 22
NGM Average fanin for LUT = 3.3705
Number of LUT symbols = 672