Problem with forever loop

[zeeekay]

Hi,

I am a newbie in FPGA. I am using xilinix ISE suite 13.1 to simulate and synthesize various examples from different books.
Currently while testing forever loop. I am getting error:

XSt:850 Unsupported Forever Statement

The Program is :

module q2(clk
);
output clk ;
reg clk;

initial
begin
clk = 1'b0 ;
forever #30 clk = ~ clk ;

end

endmodule

I have selected sparton-3E starter board in Design properties of Xilinx project design.

Kindly help me to solve the problem.

 

[abhikohli]

You are trying to use non-synthesizeable constructs. You can only use a sub-set of any HDL for writing a synthesizable code (code that can be turned into HW). I am sorry to say, but you need to go back to the basics of HDL before investing further time in using FPGAs. Statements like initial, forever etc can not be synthesized (though you can use a simulator to simulate these) hence you can not generate a clock in FPGA. (But yes, you can use it in test bench to simulate a clock generation)

 

[dll_fpga]

loops are not synthesisable unless the bound is well defined and fixed.ie forever loops are not synthesisable
search google for synthesisable contructs in xst.

Hi,

I am a newbie in FPGA. I am using xilinix ISE suite 13.1 to simulate and synthesize various examples from different books.
Currently while testing forever loop. I am getting error:

XSt:850 Unsupported Forever Statement

The Program is :

module q2(clk
);
output clk ;
reg clk;

initial
begin
clk = 1'b0 ;
forever #30 clk = ~ clk ;

end

endmodule

I have selected sparton-3E starter board in Design properties of Xilinx project design.

Kindly help me to solve the problem.

 

[abdulwahababid]

use synthesize delay(counter) instead of #(delay) if you want to try it on FPGA.
#delay will be only applicable in simulation or test bench not in any hardware like FPGA.