Problem with filters in PLL which is used to demodulate a square wave

[nidahas]

hi to all
i am using pll to demodulate a square wave .the carrier freq is 800hz where as message is 100hz.i am using simulink to design pll.i am using discrete vco ,phase detector made with flipflops.and fdatool to deign filter.however i am having problems regarding the filter.i dont know how to chose the cutoff frequeny of low pass filter.i have set it to 110 hz.is it ok???
secondly do i need to use charge pump with the flipflops??
your help ang guidance is more then needed.

 

[springf2000]

simulink reticle modulation

the cutoff frequency is about 1/10 reference frequency,it is nothing to do with the carrier frequency,i think y should read some material about the PLL

 

[biff44]

how to make a phase lock

Do you really mean hertz? That is pretty low frequency.

What modulation are you using for the 100 Hz data?

If you are using something like BPSK, sure a 110 Hz loop bandwidth will be ok. But you have to fool around with the poles and zeroes of the loop filter to make it stable. You will have a relatively large time delay component, since you only get 8 samples of carrier sine wave in which to determine what phase the carrier is at for each data period. You have a time delay of 1/800 Hz for the first sample, and then the next phase sample is delayed another 1/800 Hz in time. Such a time delay will affect how the loop filter responds. In control theory books this is called "transportation lag", and to a first order it looks like extra phase shift in the control loop. That extra phase shift tends to make the loop more unstable, so you need to do some extra stuff to insure phase margin and gain margin in the loop.

If simulink can model the complex time delay, it is like multiplying the open loop response by e^-τS. In frequency domain terms, the phase shift at a given control loop frequency is Θ = -ωτ, where your ω = 2 Π 110 (your open loop bandwidth), and τ = 1/800, or in other words, -49.5 extra degrees of phase shift in the open loop transfer function at its 0 dB crossing!

 

[nidahas]

Re: phase lock loop

thanks alot for your comments......
well its actually i am working on target position estimation using reticles and i am modelling the output signal.a reticle is basically a disc with alternate black and white spokes.as the disc rotates ,you get a narrow band fm modulated signal.the target positon is extracted from the phase and amplitude of the message sinal.which has a freq of about 100Hz.the carrier is 800Hz.inorder to demodulate the signal various techniques such as freq disciminater etc are used.however i am trying to do it with pll.i have studied various literature on PLL.but they basically talk about phase detector or vco.they only slightly talk about filter.
thanx once again.

 

[biff44]

Re: phase lock loop

Phase locked loops make pretty lousy FM demodulators, in general. That is because they are PHASE LOCKED, not frequency locked. So if your frequency changes too far and too fast, the loop will become unlocked. In communications systems, we used to use PLLs to generate an FM modulated transmit signal. We would DC couple the PLL to the VCO, but AC couple the FM modulating data. In those cases we had to make sure that the instantaneous phase angle hitting the PLL phase detector was always small, like 2Π/1000 or smaller.

So I am not sure that your scheme would qualify as a small angle system.

Have you considered actually counting the pulses in a fast dsp or microcontroller. You could gate the count with the reference, and count the actual number of pulses. I am working with a system that uses a fairly standard PIC controller that does that very easily at a 1 KHz data rate. You get very accurate counts!

 

[nidahas]

phase lock loop

thnx once again!!
pll can be used to lock freq as well phase.it all depends on the type of phase detector you use.like i am using j-k flipflops to make my phase detector.it detects both phase and frequency.

Added after 6 minutes:

its D flip flop...sorry i made a mistake while writing

 

[biff44]

Re: phase lock loop

Uh, not really. The phase frequency detector is highly non-linear when you loose phase lock. About the only thing you can say about it is that it is monotonic with frequency. ie. it eventually pushs the charge pump in the right direction so a phase lock will happen.

There are things called frequency locked loops. You would use some LC network to provide a linear output of delta F to delta V. But if you were going to do that, why bother with a PLL at all, just use the frequency discriminator and read the output voltage direct in an ADC.

 

[nidahas]

Re: phase lock loop

can u use dll for fm demodulation???if yes then how