Problem with extracted view simulation in Cadence

[mtwieg]

Hi all, I'm at the point in my design where I want to start simulating with parasitic capacitance extraction, but I've found that I've been unable to get any extracted views to simulate properly. The schematic view simulated fine, the layout passes DRC and LVS fine, and the extracted view itself looks good, but when I switch the simulation view from schematic to extracted, everything seems to break.

For example, I try to just simulate the DC OP on an LNA block in my test bench, and I get the following:


It always tells me that all my global supplies are connected to only one node (except gnd!), and it usually complains about at least one floating node (they're not actually floating). It then fails the DC analysis, unless the circuit is very simple (but the results are still totally wrong). If I look at the netlist in ADE, it shows my a netlist which does not include any references to my global supplies, instead referring to them as net0 or net1, etc. But if I descend into the extracted view and click on objects on the supply rails, it will identify them as properly connected to gnd! and vdda!

Any ideas? This is happening with every single one of my cells and I've hit a wall here.

 

[BigBoss]

Can you see extracted_view netlist when you launch ADE ?? Is it correct ?? It should be very large netlist compare to schematic view.
Second, are those global vdd! and gnd! defined in CDF of the block ?? So, vdd! and gnd! are really connected with internal nets ??

 

[mtwieg]

Can you see extracted_view netlist when you launch ADE ?? Is it correct ?? It should be very large netlist compare to schematic view.

Yes, the netlist for the extracted view looks okay as far as I can tell, except that it does not include any reference to my global nets (every terminal that should be connected to gnd! connects to _net1, and same with vdda! and _net0).

Second, are those global vdd! and gnd! defined in CDF of the block ?? So, vdd! and gnd! are really connected with internal nets ??

Not exactly sure what you mean by "the CDF of the block." I have instances of the global supply symbols in every schematic cell, and they are pins in every layout cell. But for some reason they don't seem to make it into the extracted netlist.

 

[dick_freebird]

Have you placed pin polygons on the top level gnd!/vss!/vdd!/...
nets to assert that desired connectivity? Has to be done at
the top level, lower level nets just get reassigned a number
as far as I recall seeing.

 

[mtwieg]

My top level is a testbench schematic, containing the cell under test. So the top level is only a schematic, so there are no "polygons" on it, just the supply symbols as shown in my first post. That particular cell under test has no internal hierarchy, it's just pmos and nmos devices.

I have also attempted to simulate the extracted cell without using a testbench schematic, and just opening ADE from the extracted view and applying stimulus directly. When I do this, I see vdda! and gnd! show up in my list of stimuli, but only as regular stimuli, not global ones! So I tried setting gnd! to 0V dc and vdda! to 5V dc and running it. When I do this, the simulation no longer complains about the single connections to the supplies, and it completes, but the results are still wrong, as if the supplies are not truly applied. When I try to directly see what the signals on gnd! and vdda! are it tells me that they are not kept outputs, even if I try to explicitly put them in the outputs list...

 

[dick_freebird]

The layout object that you extracted, I assume is placed in the
testbench as a symbol and the switch view list prioritizes the
extracted (I was used to using analog_extracted back in the
Diva days, forget now the extgended rigamarole that came on
with Assura extract, annotate, etc. In any case that layout
which was turned into an extracted view, must have any net
you want to access by name, pin-tagged at its uppermost
level.

This should work for globals the same as simple named nets
but if globals continue to fail you, consider pin-tagging the
global nets as simple nets and pin them out on the symbol
so as to force explicit schematic connectivity.

If you inspect your extracted netlist, are your globals' names
showing up as pervasively as you'd expect? Is there perhaps
some switch setting that decides whether to use pin polygon
names or assign self defined net naming?

I have seen the simulator refuse to keep gnd! which is always
node 0 for Spectre / Spice. I have not seen it refuse to keep
the other globals (and any net can be made global, by appending
'!' to it). Maybe try separating gnd! from your keep-list attemps
(maybe that alone is making it barf and the others just catch
a stray bullet?).

Now I am starting to vaguely recall something that annoyed me
about the Assura days, like to get a proper av_extracted or
av_analog_extracted (or whatever, it's gotten foggy) I had to
go through LVS successfully first, in order that the correspondence
of nets could be assigned. Not sure why, but I never did use the
plain extracted view and always the "refined" ones. This was how
I was told it had to be done and I never dug into "why?" since
it was a trivial nuisance in my layout / verification activity stream,
and an unverified layout has a fair chance of not being worth
simulating. Not to mention that this also ensures that you have
already a schematic view which you'd be able to debug the
testbench with beforehand. Then you can ping-pong back & forth
in a config-view based simulation and look at the differences to
debug stuff, by just changing the view-switch for one block.

 

[mtwieg]

The layout object that you extracted, I assume is placed in the
testbench as a symbol and the switch view list prioritizes the
extracted

Correct.

(I was used to using analog_extracted back in the
Diva days, forget now the extgended rigamarole that came on
with Assura extract, annotate, etc. In any case that layout
which was turned into an extracted view, must have any net
you want to access by name, pin-tagged at its uppermost
level.

Right, the layout has all the IO, including the supplies, tagged with symbolic pins. I can also see them in the extracted view (the view name is just "extracted" not analog_extracted or extracted_view).

This should work for globals the same as simple named nets
but if globals continue to fail you, consider pin-tagging the
global nets as simple nets and pin them out on the symbol
so as to force explicit schematic connectivity.

I suppose this would probably work, but that means I have to create duplicate versions of every single cell I want to test.

If you inspect your extracted netlist, are your globals' names
showing up as pervasively as you'd expect? Is there perhaps
some switch setting that decides whether to use pin polygon
names or assign self defined net naming?

I don't see any switches in the extraction options that look useful for this...

Here is what my netlist looks like if I open ADE from the extracted view and create the netlist. gnd! becomes 0, and vccd! is preserved, so it looks good (except that at the top, it does not mention that vccd! is global?). But if I try and simulate it in this view, it still does not work, as if vccd! is not actually applied.


Here is the netlist if I open ADE from the schematic view of my testbench, containing just the symbol for the cell under test, and setting the switch view to extracted. Now gnd! and vccd! are replaced with net0 and net1. At the top, it does mention my globals 0 and vccd!, but they are not connected anywhere in the netlist.


My ICFB version is v5.14.11, so it's pretty old.

 

[dick_freebird]

If you open the extracted view in the layout editor
and select the vccd! net (as you recognize it) the
selected segment should bear the netname property.
If you 'probe' it, the entire net should be picked up
(likewise). Is this the case? Or is the naming of the
net what's busted?