Problem with equivalence check (synopsys Formality)

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stevenv07

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Hello,

I have a problem with equivalence check between RTL and gate-level netlist. The problem may be related to error FM-503.
could you help me point out this issue?

Thanks in advance.

Steven
--- Updated ---

Of course, I already included *.svf file during Formality setup.
 

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I found that the pipelining with the design-ware multiplier "DW02_mult_6_stage" (Synopsys) causes this problem. I already used .svf file generated by Design Compiler during the Formality verification. However, the error still occurs.

Can anyone help me solve this issue?
 

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