Problem with delay in interface that doesn work at 150Mhz

[bjzhangwn]

about the delay

I am confused with my work,The interface I designed must work between 100Mhz and 150Mhz,now the interface work well at 100M,but if the speed is 150M,now the problem is that the extenal device didn't sample the data correctly.and the delay exceed 1 period!

 

[tom123]

Re: about the delay

I think you should place your design's input register and output register

into IO cel of FPGA, at the same time, you can use pll in fpga to improve

IO timing, that's ba big help.

I am confused with my work,The interface I designed must work between 100Mhz and 150Mhz,now the interface work well at 100M,but if the speed is 150M,now the problem is that the extenal device didn't sample the data correctly.and the delay exceed 1 period!

 

[srik_naidu]

about the delay

hi,
use buffer at the input and output of the design.

with regards,
srik