Problem with delay at turn off in an inverter

[Leafar]

Hi. I mounted in a breatboard a half bridge inverter with igbt's and the IC ir2110 to do a easy test and check if the control signal is ok and the igbt's are properly reacting to the control signal. I'm using a dspic 30f4011 to produce a pwm control setting a dead time of almost 4.5 us. However i'm getting a very odd problem. Although i'm using a pure resistive load (22 Ohms and power rail of 20 volts) when cheking the Vds of the igbt's with it's respectively gate signal i can see a delay in the turn off. That delay is of approximately 4.5 us (the same amount that dead time and it changes with dead time...) here are some photos:

High side (the upper signal is Vds the other is Vgs):
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Low side (the upper signal is Vds the other is Vgs)::
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When i look the Vds signals at the same time i can't see any dead time. I'm using a bootstrap capacitor of 22uF. And gate resistors of 27 ohms. The diode of bootstrap is a 1n4148 and i put diodes of the same reference in anti parallel with teh gate resistors. The circuit is this:

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Any ideas about what is the problem?

 

[BradtheRad]

Re: Problem with inverter

You have an N-device as the upper and lower switches. An N-device has its gate referenced to the emitter (more negative terminal).

Does the upper switch have a definite V differential between gate and emitter when it is supposed to turn on?

If the gate needs to see a low-impedance path to ground via the emitter, is there a path to ground?

I was going to suggest a P-device as the upper switch... however I see its signal comes directly from the IC, so a P-device would need a different signal.

 

[Leafar]

Re: Problem with inverter

First of all sorry and be patience if i don't understand something. English is not my first language and i'm a novice with inverters.

Does the upper switch have a definite V differential between gate and emitter when it is supposed to turn on?

Well in my circuit the gate-emitter voltage in turn on is almost 15 volts (14.8) for both igbt's. According to the datasheet of the igbt's (reference IRG4PC50UD) the gate threshold voltage has a min. of 3 volts and a max. of 6 volts. deppending of conditions as temperature so i think my circuit in that respect is ok.

If the gate needs to see a low-impedance path to ground via the emitter, is there a path to ground?

Sorry i forgot to draw in the schematic the connection between Vs in ir2110 and the middle of the bridge, but in the real circuit is ok.

However strangely when i disconnect the Vs pin of the bridge like in the schematic, the delay disappears but the current in half bridge grows rapidly burning a fuse that i put like protection in the power rail. Maybe that could be a hint of the problem.

I even tried with a drive with negative bias like the shown in this document (page 21) http://www.irf.com/technical-info/appnotes/an-978.pdf but the problem remains.

 

[FvM]

I'm unable to hear a clear problem description from your post. An I don't see an actual problem yet.

The first issue is of course, that you don't exactly tell which signals are displayed in your waveforms. I assume so far that it's low side IGBT's Vge and Vce.

It's important to understand, that the Vce waveform is created by three different elements:
- Switching of low-side IGBT
- Switching of high-side IGBT
- Load resistor (It looks however like no 22 ohm resistor is connected in the present measurement)

Considering this fact, the waveform looks plausible at first sight. Both Vce edges are apperently created by the respective low-side and high-side active Vge signal.

So what's the exact problem? How does it show in the waveform?

 

[Leafar]

Sorry you're right maybe i'm not clear enough. Let's take a look just to the first image. This image show Vce and Vge high-side IGBt signals (upper signal is Vce, bottom is Vge):

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With the yellow lines i marked the changes of Vge with respect to Vce. You can see that when Vge turns on, the igbt is turning on (Vce became 0 so the switch is closed) almost inmediately. However when Vge turns off the igbt reacts with a delay of 4.2 uS. I know this is not a "tail current" effect because that delay change when i vary the dead time in the dspic.

So when i set the deadtime to zero the delay dissapears wich is very odd to me. The same occurs in the low side.

Shouldn't the igbt's turn off with the respective Vge signal independent of dead time?

The consequence and the problem with this is that no matters how much dead time i set in the dspic, when i see Vce signals of both igbt's at the same time i don't see any dead time. That could happen with a inductive load, but no with a pure resistive load right?. What i see is that when a igbt is not totally turned off the other is almost turned on, and hence it seems there is a shoot trough.

All this makes me think that the high side Igbt is turning off with the change of the low side Vge and vice versa wich is very strange to me.

 

[FvM]

As said, the waveform looks like no load resistor connected (or a rather large value, surely not 22 ohm).

Without a load resistor, the output voltage does not change during dead time, when the IGBT is turned off. The output node is floating respectively keeps the voltage due to transistor capacitances.

Vce changes, when the other IGBT turns on. With a load resistor connected, you'll get an asymmetrical timing, because the output voltage is driven by the load resistor during dead time. But it can't be seen.

 

[Leafar]

As said, the waveform looks like no load resistor connected (or a rather large value, surely not 22 ohm).

How should it looks?

I changed the load for a resistor of 6.2 ohms. Now it seems that the high side don't have problem, but the low side looks bad. I know that the resistor is well connected because is warming up and the voltage source shows current consumption (almost 5 amperes).

Here are the images :

High side:

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It looks good. No delay between Vge, and Vce.

But the Low side:

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Is looking bad. Now there is a delay not just at turn off but at turn on (in fact is turning on before the gate signal!! it seems like is reacting with the Vge signal of high side). And the problem remains when i look Vce of both signals:

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I can't see any dead time

Any idea of what is the problem?

Regards

 

[D.A.(Tony)Stewart]

Please recheck correct values for C9 and C10. First glance I would say the bootstrap Cap is too big and C9 and C10 are reversed.

The app note says
"3a. Increase the bootstrap capacitor (CB) value to above 0.47 µF using at least one low-ESR capacitor.
This will reduce overcharging from severe VS undershoot.

3b. Use a second low-ESR capacitor from VCC to COM. As this capacitor supports both the low-side output buffer and bootstrap recharge, we recommend a value at least ten times higher than CB.

3c. Connect decoupling capacitors directly across the appropriate pins as shown in
Figure 7.

3d. If a resistor is needed in series with the bootstrap diode, verify that VB does not fall below COM, especially during start-up and extremes of frequency and duty cycle.

Granted proper application of the above guidelines, the effects of VS undershoot will be minimized at source. If the level of undershoot is still considered too high, then some reduction of dv/dt may be necessary. " Page 10

 

[FvM]

I changed the load for a resistor of 6.2 ohms. Now it seems that the high side don't have problem, but the low side looks bad. I know that the resistor is well connected because is warming up and the voltage source shows current consumption (almost 5 amperes).

If we don't look at the ringing, the switching waveform look as expectable. You see now the asymmetrical timing that I requested in post #6.

Is looking bad. Now there is a delay not just at turn off but at turn on (in fact is turning on before the gate signal!! it seems like is reacting with the Vge signal of high side).

Yes, it can't but react with the high side gate signal when you make the half bridge source an output current.

And the problem remains when i look Vce of both signals.

Very true. Both Vce measurements are basically showing the same switching waveform, differing by the constant bus voltage, and one shown inverted.

As you found out, the output waveform follows the timing of the high side gate signal. If you reverse the output current direction (connect the resistor to +30V instead of ground), you get the opposite behaviour, the output voltage will follow low side gate signal.

I hope, you'll be able to understand that there's nothing bad with the observed waveforms.

 

[Leafar]

Thanks for your help FvM. So basically all is ok (including the waveforms in the image that shows both Vce signals) except for the ringing. How can i eliminate that?

Is normal that the inverter works well with very small load values like 6.2 ohms, or 10 ohms (with this value works too) but doesn't work with 22 ohms?

So if I want to drive a motor with this ¿Must it's resistance be of approximately the value of the resistor that i used in this test (6, 10 ohms)?

Regards

 

[FvM]

Is normal that the inverter works well with very small load values like 6.2 ohms, or 10 ohms (with this value works too) but doesn't work with 22 ohms?

Working well isn't the right term. It's normal operation, that the commutation (switchover of output curent between low and high side transistor) timing varies with output current sign and magnitude. The effect becomes more complex if you change to inductive loads and different load power factors, e.g. in an AC motor inverter.

Transistor capacitances and switching time (stored charge carriers) are also influencing the waveform. But the waveform with 22 ohm resistor looks pretty much like open circuit, thus I doubt that the resistor is actually 22 ohm.

Of course there's no problem to operate the output stage without a load. But the effective duty cycle respectively output voltage changes.

 

[D.A.(Tony)Stewart]

" Use a second low-ESR capacitor from VCC to COM.we recommend a value at least ten times higher than CB."

Cb= C10= 25 uF
Ccom= C9= 1 uF

Your caps are reversed ;O

 

[FvM]

I'm unable to determine if the ringing is created in the driver or power circuit. Some details suggest, that it's mainly caused by insufficient bus voltage bypassing or circuit inductance (Difference between Vce high- and low-side measurements).

Correct driver bypassing is recommended anyway.

 

[Leafar]

" Use a second low-ESR capacitor from VCC to COM.we recommend a value at least ten times higher than CB."

Cb= C10= 25 uF
Ccom= C9= 1 uF

Your caps are reversed ;O

I changed Cb with 2.2 uF, so the signals shown in post #7 are waveforms with cb=2.2uf. But you are right i have to change Ccom according to recommendations.

Correct driver bypassing is recommended anyway.

Tomorrow I'll do some changes in bypassing and other adjusments and post the results.

Regards

 

[D.A.(Tony)Stewart]

ESR <100 mOhm and ratio of Ccom/Cb >=10 too.
Ferrite feedthru to reduce crosstalk.

 

[Leafar]

Well with better bypassing and changing Ccom to 22 uf the ringing observed was less than before. Now i have a question, if i implement a full bridge spwm inverter like this:

and according to the said by FVM:

Without a load resistor, the output voltage does not change during dead time, when the IGBT is turned off. The output node is floating respectively keeps the voltage due to transistor capacitances.

I have to be sure that always T1 than T2 are ON right? because if they don't there could be a short circuit problem with T1 and T4 (T1 doesn't turn off until T4 turns on due to transistor capacitances). How can i do that?

Another question, how can i measure dead time in a full bridge configuration?

 

[D.A.(Tony)Stewart]

You want to use a similar dead time and alternate between diagonal pairs . for creating an alternating drive level. If either bottom "XOR" top pair are on it would shunt the load quickly such as a speed brake for a motor.

 

[FvM]

I have to be sure that always T1 than T2 are ON right? because if they don't there could be a short circuit problem with T1 and T4 (T1 doesn't turn off until T4 turns on due to transistor capacitances). How can i do that?

According to the original waveforms, you have implemented plenty of deadtime in the gate signal generation. There's no reason to assume it's not suffcient.

I hear a misunderstanding in your post. A transistor capacitance keeping the voltage without any load isn't the same thing as the transistor not turning off.