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Problem with defining the Inout port in VHDL

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Vonn

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VHDL Problem

Hi all ,
I'm writing VHDL code to drive a programmable chip. My problem is that when I define the Inout port the synthiezer force it to out port . The only way to make it understand that it's an INout that you must load it by 'Z' during the code ...
My questionis , is that the only solution ??
 

Re: VHDL Problem

It is my problem too.
When I use InOut in Max+PLus II 10.2, Compilying is OK, but the wave simulation can not recognize the port.
I will post my source the board.
 

Re: VHDL Problem

xilinx ise software there isn't this problem,but i think this problem isn't from software.can you explain more,send your codes.
 

Re: VHDL Problem

Well...defining as inout doesn´t exactly mean you have a tristate pin (o;

For an output-only pin requiring feedback you also have to declare it as inout ... so if you really need a bidirectional pin than you need to use ´Z´assignment for the output code (o;

Nothing strange here...
 

Re: VHDL Problem

I guess one of the RTL rules is not to use inout ports ...
 

Re: VHDL Problem

synopsis fpga express can except:

a small skeleton if you want a bidirectional bus/port:

entity fpga is
port(
...
bus : inout Std_Logic_Vector(n downto 0);
rd_neg: in Std_Logic;
...
);
end fpga;

architecture fpga_arch of fpga is

-- signals for the internal registers
busin : Std_Logic_Vector(n downto 0);
busout : Std_Logic_Vector(n downto 0);

....
busin <= bus;
bus <= busout when rd_neg = '0' else (others => 'Z');

end fpga_arch;

if you want just a feedback from an out port, maybe, you'd better define an internal signal to avoid inout:

entity fpga is
port(
...
porty : out Std_Logic;
...
);
end fpga;

architecture fpga_arch of fpga is

porty_s : Std_Logic;

...
porty_s <= ...; -- get the out value
porty <= porty_s; -- create the output
... <= porty_s; -- use as input

end fpga_arch;
 

Re: VHDL Problem

mc&fpga said:
xilinx ise software there isn't this problem,but i think this problem isn't from software.can you explain more,send your codes.

My problem and code are here:
 

Re: VHDL Problem

Husoo said:
synopsis fpga express can except:

a small skeleton if you want a bidirectional bus/port:

entity fpga is
port(
...
bus : inout Std_Logic_Vector(n downto 0);
rd_neg: in Std_Logic;
...
);
end fpga;

architecture fpga_arch of fpga is

-- signals for the internal registers
busin : Std_Logic_Vector(n downto 0);
busout : Std_Logic_Vector(n downto 0);

....
busin <= bus;
bus <= busout when rd_neg = '0' else (others => 'Z');

end fpga_arch;

if you want just a feedback from an out port, maybe, you'd better define an internal signal to avoid inout:

entity fpga is
port(
...
porty : out Std_Logic;
...
);
end fpga;

architecture fpga_arch of fpga is

porty_s : Std_Logic;

...
porty_s <= ...; -- get the out value
porty <= porty_s; -- create the output
... <= porty_s; -- use as input

end fpga_arch;

Would you like to check my code in:


Thank you! I look forward to your reply!
 

VHDL Problem

You can search in xess.com. In this site, there are many example about the interface of CPLD or FPGA with microcontroller. This code is written by VHDL which base in Xilinx Foundation software for university but you can change it to ISE 6.2
 

Re: VHDL Problem

Thank you.
My source is compiled well, but is embarrassed in simulation only. Why?
 

Re: VHDL Problem

Inout ports are bad for heirarchal design. Try using buffer or decalare the port as out with an intermediate signal that can be tristated as well.

delay (delay by technology)
 

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