Problem with CPLD code

[pavan.emb]

Hi all,

I am doing a small program with CPLD in xilinx.(I am new to the verilog code).

Here is my program....

module f_count
(
(* LOC="P1" *) output Buzzer_out,
(* LOC="P44" *) input in_clock,
(* LOC="P43" *) input GCLK,
(* LOC="P42" *) output Output_Signal,
(* LOC="P3 P5 P6 P8 P12 P13 P14 P16 P27 P28 P29 P30 P31 P32 P33 P34" *) output [15:0]f_measurment
);
reg [15:0]count;

assign count = f_measurment;

always @(negedge in_clock)
begin


if(count[15:0] > 16)
begin
Buzzer_out = 1;
Output_Signal = 0;
end
else
begin
count <= count + 16'd1;
Buzzer_out = 0;
Output_Signal = 1;
end
end
endmodule



****

when I am synthesising this code, I am getting the error as follows........
Expecting the 'endmodule' but found 'if'.

what could be the mistake in the code...........

Thanks all.

 

[lucbra]

I assume there might be an 'end' to much. Check the if .. else ... end loops.