Problem with control signals

[sheikh]

Hello Dears
I wrote a vhdl code for this equation V= (a + b + c)*3, ( a and b and c are variables). When I simulate it, and give the registers load in test bench, it work correctly, but when I merge this code with a control unit and produce load signals with this control unit the simulation out put doesn't show the first input, except the inputs are applied after loading the input registers ( fig 2). I test my control unit and it produces the load signals in same time with when I insert load signal by hand in vhdl test code? Could you please explain where is my mistake?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity V_DataPath is
       port  (    
	           CLK              : in  STD_LOGIC;                   
	           a                : in  STD_LOGIC_VECTOR(31 downto 0);
	           b                : in  STD_LOGIC_VECTOR(31 downto 0);
	           c                : in  STD_LOGIC_VECTOR(31 downto 0);
	           L_a              : in  STD_LOGIC; 
	           L_b              : in  STD_LOGIC; 
	           L_c              : in  STD_LOGIC; 
	           L_c_1            : in  STD_LOGIC; 
	           L_C1             : in  STD_LOGIC; 
	           L_C2             : in  STD_LOGIC; 
	           L_V              : in  STD_LOGIC; 
               V_Value          : out  STD_LOGIC_VECTOR(31 downto 0)
			   ); 
End;


architecture str of V_DataPath is

-- Component Declaration.

Component LOADABLE_REGISTER
  port (
    CLK: in STD_LOGIC;
    LOAD: in STD_LOGIC;
    RESET: in STD_LOGIC;
    INPUT: in STD_LOGIC_VECTOR (31 downto 0);
    OUTPUT: out STD_LOGIC_VECTOR (31 downto 0)
  );
end Component;

-- Signal Declaration

Signal	a_Sig      : STD_LOGIC_VECTOR(31 downto 0); 
Signal  b_Sig      : STD_LOGIC_VECTOR(31 downto 0); 
Signal	c_Sig      : STD_LOGIC_VECTOR(31 downto 0); 
Signal	B_1_sig    : STD_LOGIC_VECTOR(31 downto 0); 
Signal	C1_Sig     : STD_LOGIC_VECTOR(31 downto 0);
Signal  C2_Sig     : STD_LOGIC_VECTOR(31 downto 0);
Signal	out_add_1  : STD_LOGIC_VECTOR(31 downto 0); 
Signal	out_add_2  : STD_LOGIC_VECTOR(31 downto 0);
Signal	out_mult   : STD_LOGIC_VECTOR(63 downto 0); 
Signal	out_mult_1 : STD_LOGIC_VECTOR(31 downto 0); 
Signal	V_Value_sig: STD_LOGIC_VECTOR(31 downto 0); 

-- Fix Value

Signal	a        : STD_LOGIC_VECTOR(31 downto 0) := (0 => '1',1=>'1', others =>'0');


Begin

    -- Reg_a
Reg_a     : LOADABLE_REGISTER port map
                         ( INPUT => a, Load => L_a, RESET => RESET, clk => clk, OUTPUT => a_Sig
						 );	
	
	
    -- Reg_b
Reg_b     : LOADABLE_REGISTER port map
                         ( INPUT => b, Load => L_b, RESET => RESET, clk => clk, OUTPUT => b_Sig
						 );	

						 
    -- Reg_c
Reg_c     : LOADABLE_REGISTER port map
                         ( INPUT => c, Load => L_c, RESET => RESET, clk => clk, OUTPUT => c_Sig
						 );	
						 
						 
    -- 1st ADD

out_add_1 <= a_Sig + b_Sig;
						 
						 
		
		
    -- Reg_c_1
Reg_c_1     : LOADABLE_REGISTER port map
                         ( INPUT => c_Sig, Load => L_c_1, RESET => RESET, clk => clk, OUTPUT => c_1_sig
						 );	

    -- Reg_C1
Reg_C1     : LOADABLE_REGISTER port map
                         ( INPUT => out_add_1, Load => L_C1, RESET => RESET, clk => clk, OUTPUT => C1_sig
						 );	

    -- 2nd ADD

out_add_2 <= c_1_sig + C1_sig;
	



    -- Reg_C2
Reg_C2     : LOADABLE_REGISTER port map
                         ( INPUT => out_add_2, Load => L_C2, RESET => RESET, clk => clk, OUTPUT => C2_sig
						 );	


    -- 1st multiplier

out_mult <= C2_sig * a;
out_mult_1 <= out_mult (31 downto 0);




    -- Reg_V
Reg_V      : LOADABLE_REGISTER port map
                         ( INPUT => out_mult_1, Load => L_V, RESET => RESET, clk => clk, OUTPUT => V_Value
						 );						 
End str;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity V_controller is
  Port ( CLR          : in   STD_LOGIC;
         CLK          : in   STD_LOGIC;
         END_Frame    : in   STD_LOGIC;
         L_a          : out  STD_LOGIC; 
         L_b          : out  STD_LOGIC; 
         L_c          : out  STD_LOGIC;
         L_c_1        : out  STD_LOGIC;
         L_C1         : out  STD_LOGIC; 
         L_C2         : out  STD_LOGIC; 		 
         L_V          : out  STD_LOGIC;
         RESULT_READY : out STD_LOGIC		 
		 );
end V_controller;
	 
architecture  state_machine of 	V_controller is 
	 
  TYPE TYPE_STATE is (RESET, T0, T1, T2, T3, FINISH);

  signal next_state    : TYPE_STATE;
  signal present_state : TYPE_STATE;	 
	 
                               ----- States Signals -----
  signal T0_state  : STD_LOGIC;
  signal T1_state  : STD_LOGIC;
  signal T2_state  : STD_LOGIC;
  signal T3_state  : STD_LOGIC;	 
	 
begin
  ------------------------------ sequential part of state machine -----------------
  sequential : process(CLK, next_state, CLR)
  begin
    if(CLR = '1')then
      present_state <= RESET;
    elsif(CLK = '1' and CLK'event)then
      present_state <= next_state;
    end if;
  end process sequential;	 
	 
  ------------------------ combinational part of state machine---------------------

  combinational : process(END_Frame, present_state)
  begin
    case present_state is
      when RESET =>
        next_state  <= T0;
      when T0 =>
        next_state <= T1;
      when T1 =>
        next_state <= T2;
      when T2 =>
        next_state <= T3;   
	  when T3 =>
	    if (END_Frame = '1' ) THEN
		    next_state <= FINISH;
		else
		   next_state  <= T3;
		end if;
     when FINISH =>
        next_state <= FINISH;
     when others =>
        next_state <= FINISH;
    end case;
  end process combinational;	 
	 
             --- signal assignment ---
  
  T0_state    <= '1' when (present_state = T0)  else '0'; 
  T1_state    <= '1' when (present_state = T1)  else '0'; 
  T2_state    <= '1' when (present_state = T2)  else '0'; 
  T3_state    <= '1' when (present_state = T3)  else '0';	 
	 
	 
              --- Load Sequences ---

  L_a       <= T0_State or T1_State or T2_State or T3_State;
  L_b       <= T0_State or T1_State or T2_State or T3_State;
  L_c       <= T0_State or T1_State or T2_State or T3_State;
 	 
  L_c_1     <= T1_State or T2_State or T3_State;	 
  L_C1      <= T1_State or T2_State or T3_State;

  
  L_C2      <= T2_State or T3_State;

  
  L_V       <= T3_State;	 
	 
RESULT_READY <= '1' when (present_state = FINISH) else '0';
 end state_machine;

 

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sheikh,

The root cause of your problem, I believe, stems from your test bench. You are experiencing a simulation scheduling failure caused by the way you applied your stimulus vectors. Look at the waveforms and you will see that the first output is asserted at the clock where the inputs go active for the subunit tb, but in the controller simulation they go active in the following clock cycle.

To fix this add a small amount of delay to the signals driving the uut in your subunit tb, e.g. For 10ns clock period add 1ns of delay to all signals driven by the tb.

After you do that both simulations will behave the same, unfortunate broken, as you you have a design error in the subunit, which was compensating for the simulator scheduling problem.

Hope this is clear enough to help put you on the right track. I'm not going to give you the fix for your code as this looks like a homework assignment.

Best regards,
-alan

 

[sheikh]

Thanks a lot dear alan
I did it ("10ns clock period add 1ns of delay to all signals driven by the tb" ) and the result was true ) . Another thing: Is it a problem for real implementation ( on fpga )? I mean ,I solved the problem by a little delay but in a real system how can I insert inputs from a specific source by desired delay?
(Indeed it isn't my homework ;D I just try to learn )
Thanks in advance
Mostafa

 

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Another thing: Is it a problem for real implementation ( on fpga )? I mean ,I solved the problem by a little delay but in a real system how can I insert inputs from a specific source by desired delay?

Mostafa,

In a real implementation as long as you have proper clock constraints and those inputs are on the same or some related clock domain, then the implementation tools will account for the setup and hold times to the module and attempt to meet timing. If those inputs are driven by logic external to the FPGA, then you would need to add input constraints for the I/Os that drive the module.

Take a look at either Altera's or Xilinx's Constraint system user guides. Altera uses SDC and Xlilinx uses it's own homegrown constraint system in ISE and a flavor of SDC in Vivado (finally).

Hope that clears things up for you.

Regards,
-alan

 

[sheikh]

Thanks Dear alan, Yes it was clear as like as the first one.