Problem with configuring divided clock that uses flip-flop in CTS

[origip]

I have a divided clock that using a FlipFlop !
But when I use Astro to do CTS, I can't configure it properly.
I use the command below:
create_generated_clock clock_1 -source clock_0 -divide_by 2 {my_flipflop/Q}
Is there anything wrong ?
Help!~~~~~

-_-0

 

[my_ego]

clock tree exclude pins

Since Astro can't get the clock tree through a FlipFlop, I am trying to replace the FlipFlop with a Mux to get the clock tree. After CTS, I will get the FlipFlop back with ECO. Is there any problem with my solution ?
My Astro is the 0309 edition !

 

[haosg]

generated clock from mux

I have a divided clock that using a FlipFlop !
But when I use Astro to do CTS, I can't configure it properly.
I use the command below:
create_generated_clock clock_1 -source clock_0 -divide_by 2 {my_flipflop/Q}
Is there anything wrong ?
Help!~~~~~

-_-0

Can show the failuer information?
by my experience, if you first do CTS for the generated clock clock_1, then
do CTS for the clock_0 , it is ok. clock_0's tree would include clock_1's tree.
all are ballance.
if you simultaniously do CTS for clock_0 and clock_1, you could not get completely balance tree.

 

[arunragavan]

create_generate_clock with different source clock

i have tutorials on CTS.. if u need it , i shall post it..

with regards,

 

[origip]

tutorial clock cts eco

The problem is like this :
I have a source clock (called ClockIn).It generates two clock for different clock domain.One is faster (called ClockFast),the other is slower (called ClockSlow).These two clocks is both configurable ,that is to say they both have a divide parameter with the ClockIn.
To simplify the question ,I set the ClockFast the same frequency as ClockIn,and set the ClockSlow half speed of the ClockIn.
When I do CTS with Astro 0309, I found that it can't get the correct clock tree.The clock tree stops at the FlipFlop(MyDividerFF) which is used to generate the ClockSlow.I generate the half speed clock simply by using this FlipFlop to feedback the output pin (Q) to its input pin (D),and set the clock of the FlipFlop (CK) with the ClockIn.
I tried to ignore input pin of MyDividerFF.Astro still can't get the clock tree from the CK to the Q, is there any problem in my design?
Because the domains of ClockFast and the ClockSlow have to exchange data frequently, so I want to do the two clock stimutenaously. What should I do?

Thank u !

 

[my_ego]

cts problem

Yeah!
The FlipFlop method to generate 2,4,6,8... divided clock is the simplest way, also stable.
But is there any other better way to do so ?
Such as using combinational logic !
Really want to know !!

 

[hgby2209]

exclude pin in clock tree synthesis

Hi!! arunragavan,

I need the CTS tutorials!! ould you please post it, thanks!!

 

[jaxshai]

create_generate_clock

Hi!! arunragavan,

You will be appreciated for the CTS tutorials .^_^

Cheers
Jaxshai

 

[sudhirtj]

generated clock scan exclude

Hi Origip,

Define the clock pin from the output of the ClockSlow flop using get_pins in your create_clock and not in the create_generate_clock. It should work.

Sudhir

 

[kctang]

Re: CTS Problem !!! Help ! Help !!!!!!!!!!!!!!!

If the duty cycle of clock signal is not important in your design, you can
use active gating technique to do clock divide. The /1 clock is the
original clock, a generated clock gating signal "ANDed" with your original
clock is the divided clock.

One advantage of this approach is both divided and non-divided clocks
can be treated as same clock tree with gated branch. However, if you've
to do DFT, then a bypass mode must be added to disable clock gating
during scan test.

 

[arunragavan]

Re: CTS Problem !!! Help

Hey guys ive posted the tutorials.. hope this helps..

sorry took some time to see the posts

with regards,

 

[haosg]

Re: CTS Problem !!! Help

!!!!

In this case, you should create_generated_clock with -master_source but -source.
Because you create two clock in one input port. if you with -source,
Astro don't know what clock is realy source of the generated clock.

 

[floatgrass]

Re: CTS Problem !!! Help

you should let tools exclude the flip-flop d pin.

 

[cxx216]

Re: CTS Problem !!! Help

I have a divided clock that using a FlipFlop !
But when I use Astro to do CTS, I can't configure it properly.
I use the command below:
create_generated_clock clock_1 -source clock_0 -divide_by 2 {my_flipflop/Q}
Is there anything wrong ?
Help!~~~~~

-_-0

Did you have solve it?
How have you solve it?I have the same problem,too!
with regards!

 

[cihchenlin]

CTS Problem !!! Help

i have the samp pro too,thanks

 

[iwpia50s]

CTS Problem !!! Help

While this may be a simple error, you should use QBar, not Q to feedback into D.

 

[shankarmit]

Re: CTS Problem !!! Help

When a flop Q pin is declared as clock clk2 then the clock clk1 of the fliplop will propagate thats why u will get problems.

U can declare a ignore pin or stop pin and do cts for clock clk1.

Then do for clk2 separetly...

This problem occurs when u design divider circuits.

Thanks

Shankar