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Problem with close loop track and hold circuit

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Syukri

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Track & Hold Circuit

I'm using close loop track and hold circuit...

The circuit use 2 analog buffer before the sample capacitance and after it.

On the analog buffer design firstly I've used ideal current source to trigger the tail current. the value is 100µA.

Then i get dynamic range between 0.04V to 3.221V.

Then in order to fabricate it is put pMOS current source ( as Resistor ) and current mirror circuit. The current source given 100µA so do the current Id for both current mirror nMOS.

But the dynamic range decrase. The top voltage still at 3.22V but the botto one is at 0.3V. This is unacceptable..

Can anyone help me....

p/s: analog buffer architecture is almost like differential amplifier.
 

Re: Track & Hold Circuit

Syukri said:
I'm using close loop track and hold circuit...

The circuit use 2 analog buffer before the sample capacitance and after it.

On the analog buffer design firstly I've used ideal current source to trigger the tail current. the value is 100µA.

Then i get dynamic range between 0.04V to 3.221V.

Then in order to fabricate it is put pMOS current source ( as Resistor ) and current mirror circuit. The current source given 100µA so do the current Id for both current mirror nMOS.

But the dynamic range decrase. The top voltage still at 3.22V but the botto one is at 0.3V. This is unacceptable..

Can anyone help me....

p/s: analog buffer architecture is almost like differential amplifier.

Hi, Syukri
Maybe you should use both nmos diff paires and pmos diff paires in parallel as the input stage to get a rail-to-rail input range. The ideal current source has infinite output resistor but the real current mirror has a finit output resistor. With the decreasing of the input voltage, the transistor served as tail current will leave out the saturation region and enter the resistor region.
sixth
 

Re: Track & Hold Circuit

can u show us the circuit so that it will be easier to suggest an improvement to your existing circuit.

regards
 

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