[SOLVED] Problem with black box in Matlab System generator

[Serwan Bamerni]

I using Xilinx system generator blocks in Matlab.

I simply using only a black box with a gateway in and gateway out.

The code for the black box is very simple and work correctly with ISE design suite

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;

entity test44_vhdl is
    Port ( row : in  std_logic_vector (1 downto 0);
           slice : out  std_logic_vector (3 downto 0));
end test44_vhdl;

architecture Behavioral of test44_vhdl is

type oneD is array (1 to 3) of integer range 0 to 15;
constant table: oneD := (3, 9, 13);

begin

    slice <= std_logic_vector(to_unsigned(table(to_integer(unsigned(row))), slice'length));

end Behavioral;

but unfortunately it doesn't work with the matlab system generator.

I got the following error message

Exception: ISE Simulator Simulation failed during initialization.

can any one help me what is the wrong with this code and what change should I do so the model work correctly

 

[TrickyDicky]

Are you sure that is the only message?

- - - Updated - - -

PS. If row comes in as "00", you will have an error during simulation as the table you have doesnt have an entry for 0. When the design is elaborated, unless you initialise the connection to row otherwise, it will start as "UU" which will get converted to "00" during the table lookup, causing an error.

 

[Serwan Bamerni]

thank you brother for your reply

you right, I don't have a value assigned to the table when row is "00"

I just assign a value to the table at 00 and now the model work correctly

type oneD is array (0 to 3) of integer range 0 to 15;
constant table: oneD := (3, 9, 13, 6);