Pobyms
Newbie level 6
I have a mixed signal design with cells connected to VCC and GND and logic gates with global pins (VCC! and GND!). In the layout VCC is connected to VCC! and GND is connected to GND!. I run the LVS using the joinNets switch for the schematic:
joinNets( root "GND!" "GND" )
joinNets( root "VCC!" "VCC" )
The LVS is clean. I run the RCX (only C) and get the av_extracted view. The parasitic caps are there and their values seem to be OK but when I try to simulate this view it does not work. In the netlist I see a problem with the VCC pin. Do I have to use any switch in the RCX form as I use the joinNets for the LVS?
Thanks.
joinNets( root "GND!" "GND" )
joinNets( root "VCC!" "VCC" )
The LVS is clean. I run the RCX (only C) and get the av_extracted view. The parasitic caps are there and their values seem to be OK but when I try to simulate this view it does not work. In the netlist I see a problem with the VCC pin. Do I have to use any switch in the RCX form as I use the joinNets for the LVS?
Thanks.