Problem with assigning among different sized arrays in verilog

[QMA]

Dear all
please help me regarding assigning arrays mutually of different sizes in verilog for xilinx. for example array xyz[3:0] is assigned to abc[4:0]. xyz has 4 bit value while abc has 5 bit value. it is not giving me actual results.

 

[TrickyDicky]

why not show the WHOLE code that is not working..

 

[dipin]

hi,

Dear all
please help me regarding assigning arrays mutually of different sizes in verilog for xilinx. for example array xyz[3:0] is assigned to abc[4:0]. xyz has 4 bit value while abc has 5 bit value. it is not giving me actual results.

its based up on your code.like trickydicky said better to show your code.

you can assign like this ::abc <= {0,xyz};
that zero is to fill the extra bit on abc.otherwise there will be some junk value in abc which will give in correct results.
or else i think if you initialize the abc to zero will solve the problem. for this there should't be any further assignment to abc excepts the inputs.

thanks & regards