problem with assign in verilog

[gmish27]

what's wrong with the following code:

module test
(
input a,b,c,
output y
);

wire x;
assign y = a & x;
assign x = b & c;

endmodule

it synthesizes and simulates too but I read their will be a mis-match between the pre and post synthesis. care to explain???

 

[dcreddy1980]

Just wanted to know where u have read or can you attach the doc which supports your statement.

I really don't see any issue with the above code.

 

[kamalkundu]

I also tried with vcs and did not found any problem and I also did not see any change after synthesis. its remains 2-input AND.

 

[chandrasg]

Not in this case. If you try using non-blocking assignments in always loop with clock you may see the difference.

 

[ljxpjpjljx]

yes, try to use non-blocking method in you assign statement!