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Problem with adding of pull-up in Edit Constraints in VHDL

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frantak

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VHDL question

Hello,
I am writing VHDL code in ISE Web Pack 5.1 for Xilinx Cool Runner II (XC2C256). I have problem with addind of pullup in Edit Constrains. The compiler wrotes that the pin has conflict with keeper. Does anybody can advise me. Thanks.
Frantak
 

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