[SOLVED] problem with ACK on I2C

[burningmosfet]

Hello everybody I am trying to interface a Texas Instruments MSP430F2618 via I2C bus with a RTC (maxim DS1337). The entire system is powered at 3V and pull-up resistors on SDA and SCL lines are 3.3k ohm.
For the I2C I'm using the libraries provided directly from Texas Instruments but I have an awful acknowledge signal from the RTC (as if something, the MCU?, is trying to keep the line low).
This happens in all the frequency range (f I2c 10k to 400k) and doesn't change considerably variing the pull up resistors on SDA and SCL.
The pics from my oscilloscope is in the first link. In your opinion, what's the problem?

Image with small acknowledge signal
**broken link removed**

Link to USCI I2C Master docs:
https://www.ti.com/litv/pdf/slaa382

Link to USCI I2C Sources:
https://www.ti.com/litv/zip/slaa382

 

[FvM]

I'm not sure, if you know, that the acknowlege is active low.

There's no problem with the acknowledge signal. The short spike occurs, because the master releases SDA before the slave sends the acknowledge, which is normal I2C operation. The only requirement in this respect is that the master has to guarantee a non-negative hold time for SDA relative to SCL falling edge, which is apparently the case. The slave has to achieve a SDA setup time of 250 ns before SCL rising edge, which is also correct.

 

[burningmosfet]

FvM Thank you very much for your rapid answer!

I'm not sure, if you know, that the acknowlege is active low. There's no problem with the acknowledge signal. The short spike occurs, because the master releases SDA before the slave sends the acknowledge, which is normal I2C operation.

You are right, the ack is active low because all lines are open drain/open collector but i think the acknowledge from rtc should be on the rising edge of the ninth clock not at the end of the byte; in this way there should be a larger pulse! :sad:.... Is there something wrong with my reasoning?

The only requirement in this respect is that the master has to guarantee a non-negative hold time for SDA relative to SCL falling edge, which is apparently the case.

Ok, it's my case.

The slave has to achieve a SDA setup time of 250 ns before SCL rising edge, which is also correct.

If i didn't misunderstood you are saying that, to avoid the filtering of ack from the microcontroller, the slave must keep the SDA line low for more than 250ns before the rising edge of ninth clock of SCL.

Is there something wrong?

 

[FvM]

To send acknowledge, SDA must be kept low between the red lines. As you can see, it's done correctly.

 

[burningmosfet]

To send acknowledge, SDA must be kept low between the red lines. As you can see, it's done correctly.

Ok thank you very much, now i can delete a line on my trouble list