Hello everyone,
im newbie in here and this is my first question. here we go
this is a two bit fulladder homework for ise xilinx
when im trying to test with UUT i see summary 0 is ok but summary-1(s0 s1) is that Z because of never used a1 and b1
whats wrong with it? note:this code works for 1 bit adder
Main programme:
There is no reason to declare an output as a reg unless it is being driven in an always block or initial block. It is not syntactically correct to declare the outputs to be a reg in this example.
thx guys everone but it didnt work
@saurabhs i tried your way but again answer is a(1) b(1) not used
@vijayiyer i ve thought like mux_master
@muxmaster your site is very helpful but i cant deal with hiearchical design why we use [4:0] in sum instead of [3:0] like a or b??
if i solve this problem, then i'll write
Is there any different idea? Bye
They use sum [4:0] for a carry out bit. u can use sum [3:0] and a different carryout bit.
For a 2 bit full adder u have to have 4 half adder. so i feel a[1] and b[1] will use in another half adder. Isn't it.I m getting u correct.
It is [4:0] because if you add together two 4 bit numbers, you may get a 5 bit number. Consider the case of 0xF + 0x1. The solution to this is 0x10 which is 5 bits. There are a couple of ways of dealing with this. One way is to set an overflow bit. Another way is to have the output be one bit larger.