Problem with 4-bit ALU Design

[Digit0001]

Hi

i am having trouble designing a truth table for the 4-bit ALU. The document details the specifications:View attachment Lab1part3.doc

My problem is how would i combine the arithmetic table with the logic table into one table? The only way i can think of is do it in separate tables
This is what i have in code:

process(A,B,sel,sCIN,cIN)
		begin
			case sel is
				when "00" => H <= A AND B;
				when "01" => H <= A OR B;
				when "10" => H <= A XOR B;
				when "11" => H <= A XNOR B;
				when others => null;
		end case;

		case sCIN is --sCIN <= sel & cin
				when "000" => G <= ('0' & A) + '0';
				when "001" => G <= ('0' & A) + '1';
				when "010" => G <= ('0' & A) + ('0' & B);
				when "011" => G <= ('0' & A) + ('0' & B) + cIN;
				when "100" => G <= (('0' & A) + (NOT B));
				when "101" => G <= ((NOT ('0' & B)) + ('0' & A) + '1');
				when "110" => G <= ((NOT ('0' & A)) + ('0' & B));
				when "111" => G <= ((NOT ('0' & A)) + ('0' & B) + '1');
				when others => null;
		end case;

P.S

 

[amitjagtap]

This can be done easily,
What i feel is you can club some of the operations like XOR, ADD: A+B and even A+1, A+B+cin, A-B these are all full adder dependent operations... Lets say you have implemented full adder for A+B+Cin then for A+B select Cin=0, for A+1 select B=1 and Cin =0, for A-B provide B's 2's complement etc...Imagine all this at RTL level...using muxes, registers, adder .
well, Dont you think shift operations should be there in ALU...

 

[Digit0001]

lets say i still want to keep the operation in tack, would i still require two case statements for the tables

 

[yanzixuan]

Hi

i am having trouble designing a truth table for the 4-bit ALU. The document details the specifications:View attachment 53446

My problem is how would i combine the arithmetic table with the logic table into one table? The only way i can think of is do it in separate tables
This is what i have in code:

process(A,B,sel,sCIN,cIN)
		begin
			case sel is
				when "00" => H <= A AND B;
				when "01" => H <= A OR B;
				when "10" => H <= A XOR B;
				when "11" => H <= A XNOR B;
				when others => null;
		end case;

		case sCIN is --sCIN <= sel & cin
				when "000" => G <= ('0' & A) + '0';
				when "001" => G <= ('0' & A) + '1';
				when "010" => G <= ('0' & A) + ('0' & B);
				when "011" => G <= ('0' & A) + ('0' & B) + cIN;
				when "100" => G <= (('0' & A) + (NOT B));
				when "101" => G <= ((NOT ('0' & B)) + ('0' & A) + '1');
				when "110" => G <= ((NOT ('0' & A)) + ('0' & B));
				when "111" => G <= ((NOT ('0' & A)) + ('0' & B) + '1');
				when others => null;
		end case;

P.S

you have two choices:
1:write a new table combine two table into one
2:let a mux switch the output and let M select it.