Problem wirh DDR SDRAM controller targeting on board XUPV2P, Virtex-II Pro

[connit1986]

I’m implementing DDR SDRAM controller targeting on board xupv2p, virtex-II pro. DDR SDRAM: KVR400x64C3A/256 256MB
I have modulated with modelsim at all levels to “post and route” with model ddr.v of Xilinx and I received good result (be able to write and read). But I had trouble while targeting on board. I used chipscope to observe and I don’t see result while reading (ddr_dq: data when read; ddr_dqs: stroble ).
Currently, I suspect that: ddr sdram with range of clock: 5ns-10ns; but board supports max 100MHZ. I use DCM to make output clk2x with clock input 100MHZ. Could you please give me some advices where I did wrong and how to repair it. Thank you very much for your time.

 

[BlackOps]

DDR question

Your controller must also supplu DDR clock to your memory chip, and that should be an output from the DDR flip-flop which must be instantiated in your VHDL code.

refer here:
**broken link removed**

 

[aftermorning]

DDR question

you can try your ddr controller at a lower freq to see whether it can work well.