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problem while using cadence calculator DFT

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coffeelox

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edaboard coffeelox

Hi there,

I am trying to measure my 10 bits ADC ENOB.

My input signal is 7.5KHz sine wave, sampling frequency is around 552KHz (required by application). And output is the sampled data through dac (written in veriloga, no filter).

First, I selected my input signal and do the DFT as,

From 30u to 1m (did transient simulation from 0 to 1ms),
number of samples 4096
window type Rectangular
smoothing factor 1
coherent gain default
coherent gain factor 1

then select dB20, I got the graph located at right in red. Why it is not just one vertical line located at 7.5KHz?

Second, I selected my output and do the DFT exactly same as above and got the graph at right in blue.

It seems that my input signal is not good and output signal is not good as well. Based on SNR = 6.02ENOB + 1.76, I could not get ENOB close to 10 bits. However, from its time domain signal plot, it seems not bad (left top is input signal, left bottom is dac output).

Why? did I make something wrong?

Thanks...

JS
 

erikl

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calculator dft cadence

coffeelox said:
... I got the graph located at right in red. Why it is not just one vertical line located at 7.5KHz?
... It seems that my input signal is not good
Your input signal is quite good, shown by the smooth decline in frequency, which is standard for rectangular (or triangular) windowing.
The frequency spectrum is generated by the very nature (algorithm) of the Fourier Analysis (convolution of the input signal with the spectrum of the sampling time points), see e.g. Ken Kundert: "The Designer's Guide to SPICE & SPECTRE", Chapt. 5: Fourier Analysis, 5.3.4.1 Windowing.
Nothing wrong, don't worry, be happy! ;-)

coffeelox said:
Second, I selected my output and do the DFT exactly same as above and got the graph at right in blue.

... output signal is not good as well. Based on SNR = 6.02ENOB + 1.76, I could not get ENOB close to 10 bits. However, from its time domain signal plot, it seems not bad (left top is input signal, left bottom is dac output).

Why? did I make something wrong?
Perhaps a little bit, but it's not too bad: Up to my ADC experience it is normal to get ENOB ≈ NOB-1 in preLayout (schematic) simulation, and ENOB ≈ NOB-2 in postLayout simulation and for the real product, even ENOB ≈ NOB-3 for 12-bit and higher resolution ADCs.

BTW: Try to make your sampling frequency an integer multiple of your input frequency, resp. the other way round, e.g. input freq. = sampl.freq. / 74 ≈ 7.459kHz . By this, you avoid artefact errors from fourier integration, e.g. interpolation errors.

HTH! erikl
 

coffeelox

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dft cadence frequency

Hi erikl ,

Thanks for your response! But I still don't understand why the DFT result for input signal does not show the graph as spike on 7.5KHz, and all other frequencies are low level flat?

Also, my input signal is 7.5KHz, however in DFT, it shows around 7.25KHz?

Thanks...
 

JoannesPaulus

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dft of a signal cadence calculator

First of all, you do not need to have an ideal DAC to calculate the SNR of your ADC. You can just add the output bits with their correct weight in the calculator and divide the sum by the power supply voltage, i.e. (VT("/b<0>)+2*VT("/b<1>)+ ... +512*VT("/b<9>))/3.3 (where 3.3 is - for instance your power supply voltage). Then, you can do the DFT of the above formula.

Now, to your question: You have 7.5 cycles of your input signal in your 4096 samples. Your input signal does not fall into one DFT bin only (that's why you see a number of tones around your tone).

You need to have an integer number of input cycles (coherent sampling). The best method is to choose fin as follows:

fin=D*fs/N

where D is a convenient odd number, fs is your sampling rate, and N is the number of samples. In your case, I would choose: D=55, fs=552kHz and N=4096 giving you a fin=7.412kHz, close enough...

I hope this helps!
 

coffeelox

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cadence adc simulation snr dft

Hi Joannes,

do you mean if using coherent sampling, only dedicated fin to dedicated fs can be used to get a perfect spectrum plot? fin/fs should be equal to Ncycle/ Nsamples?

it seems like different concept as fourier transform then?

Thanks...
 

JoannesPaulus

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cadence calculator

coffeelox said:
do you mean if using coherent sampling, only dedicated fin to dedicated fs can be used to get a perfect spectrum plot? fin/fs should be equal to Ncycle/ Nsamples?
If you use rectangular windowing, that is correct. If you use windowing, you can use any frequency but then you will have spectral leakage that depends on the window you choose.
Moreover, choosing the ratio D/N correctly will enable you to run the shortest simulation possible (it will be very handy when you run post-layout extracted simulations...).
 

coffeelox

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cadence calculator spice

Thanks for the response.

However, I am still not very clear about the DFT and ENOB. If I did not run coherent sampling, then how can I based on the DFT plot to get ENOB? it seems that SNR = 6.02ENOB+1.76 is not valid as the SNR is not the SNR I want (due to spectral leakage, SNR got worse result). Maybe only coherent sampling is allowed to measure ENOB?

Thanks..
 

JoannesPaulus

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cadence calculator

Well, garbage in garbage out...
Can't you re-run the simulation?
At any rate, you can still figure out something. Your output seems to be about 5dB below full scale (if your DAC is implemented correctly) while your input seems at 0dB. So you need to add 5dB to your ENOB (almost 1 bit!).
 

coffeelox

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fourier transform in cadence

yes, I can rerun the simulation. However due to big distance between fin and fs, I will have to run many cycles (128) which will cost me almost 6 hrs on it. :cry:
 

JoannesPaulus

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using dft in cadence

If you look at my previous posts, you only need to run your simulation for 55 cycles! ...plus some for settling of the references... So, your simulation will only be 3hrs...
 

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