Problem while locking PLL

[vasusathiyam]

Here i attached the control voltage to the VCO of PLL.

From this i know my PLL(2nd order PLL) is going to lock that is the input of the VCO well known from PSS analysis.

But i got some oscillation while locking the phase of the signal(2nd wave)

(Measured by delta cursor i got 500MHz but in calculator not coming)


Can anyone explain the reason where is the problem?

 

[genius1990]

pls check with the resistor used in the circuit part....coz their variation could result in variation in locking range..

 

[zorro]

Hi vasusathiyam,

It seems a random fluctuation around the lock condition.
Have you checked the phase noise of your design?
Are this figures from measurement or from simulation?
Regards

Z

 

[vasusathiyam]

Thanks for all.

we get it from simulation only

Phase noise is for total PLL or only VCO

 

[zorro]

we get it from simulation only

Then, you can try to remove any noise source from the simulation model. You should observe a stable steady-state, perhaps with a noticeable small ripple coming from the phase comparator.
Regards

Z