Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

problem: to_ufixed(0.483,n1)

Status
Not open for further replies.

fanwel

Full Member level 3
Joined
May 26, 2011
Messages
178
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Activity points
2,878
Hi all;

I want to convert 0.483 to ufixed type. Manually, I get 0000.0111 (3 downto -4) when I calculate by hand.
But, this value is not same with the value in modelsim which is 0000.1000. I write like this;

ip1<=to_ufixed(0.483,n1);

What the correct value of 0.483 in ufixed? Do I calculate in wrong way?..needs help, thanks
 

0.483 x 2^4 = 7.728 which is 8 (1000) when you round to nearest.

to_ufixed has extra options for saturation and rounding you can add to the function.
 

Sorry, what actually the formula to convert to ufixed? thanks for reply
 

Y x 2^f, where f is the number of fractional bits.

This will give you the number you can easily convert to binary.
 
  • Like
Reactions: fanwel

    fanwel

    Points: 2
    Helpful Answer Positive Rating
I try write a code for convert integer to ufixed:

package my_data_types is
type vector is array (natural range <>) of integer;
type ufixed is array (natural range <>) of std_logic;
end my_data_types;

library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use work.my_data_types.all;

entity fix is
port (clk: in bit;
nprev: in vector (0 to 7);
ip1: out ufixed (3 downto -4));
end fix;

architecture fix of fix is
signal n1: ufixed (3 downto -4);
begin
process(clk)
begin
if (clk'event and clk='1') then
for i in 0 to 7 loop
ip1(i) <= to_ufixed (nprev(i),n1);
end loop;
end if;
end process;
end fix;

I get this error:
Error (10482): VHDL error at fix.vhd(3): object "std_logic" is used but not declared.

How to declare the "std_logic" in package?..
 

you forgot to include the std_logic library

library ieee;
use ieee.std_logic_1164.all;

---------- Post added at 11:30 ---------- Previous post was at 11:29 ----------

Also, a big big big note:

DO NOT DECLARE UFIXED. It is in the fixed_pkg.
 

What the right way to declare ufixed as an array?..thanks for reply
 

you dont need to define ufixed, it is already in the fixed_pkg.

so you you need to do is:

Code:
library floatfixlib; --(or IEEE_PROPOSED if you're using an older version)
use floatfixlib.fixed_pkg.all;

.....
signal a : ufixed(10 downto -27);

...etc
 

Now I get this error:
Error (10511): VHDL Qualified Expression error at fix.vhd(23): to_ufixed type specified in Qualified Expression must match std_ulogic type that is implied for expression by context.
At this line: ip1(i) <= to_ufixed (nprev(i),n1);

What my mistake?..thanks for reply
 

ip1(i) is a single bit. You cannot assign an entire array (the ufixed) to a single bit.

You need to decalre an array of ufixed values.
 
  • Like
Reactions: fanwel

    fanwel

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top