On the CAPTURE DR state the data register is loaded and the data register shifts data (TDI-DR-TDO) as long as it stays in the SHIFT_DR state with TMS = 0. If the DR is 16-bits then you keep TMS low for 16 TCK. The entire FSM is controlled by TMS.
It's used during production for checking connectivity of parts on a PCB
Both during production or after for programming devices, for debugging, and as interfaces to FPGAs, CPLDs, uP, etc.
e.g. We use JTAG to program Microsemi FPGAs in our production floor, JTAG to program prototype Xilinx boards in the lab, and debug Xilinx boards after production runs when problems are found and need to be debugged.