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# problem of calculating setup and hold time

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#### sowmya005

##### Member level 5
setup time

Hi friends,
I have a problem of calculating hold time.
A flipflop has a combo of delay td in the data path and
a combo of delay tc in the clock path.
If this becomes a new flop with input of the combo in the data path becomes new D pin and input of combo in clock path becomes new clock pin,
the output Q remains same.
what is the relation between the old hold time and the new hold time?
Can we find the relation between the old setup time and the new setup time also?

setup hold time

Hi friends,
I found the answer by myself.
A positive setup time indicates a time before the active edge of clock, a negative setup time, after.

(setup time at pin of whole chip) =
(setup time of flip-flop data pin)
- (min clock delay from chip pin to FF pin)
+ (max data delay from chip pin to FF pin)

A positive hold time indicates a time after the active edge of clock, a negative hold time, before.

(hold time at pin of whole chip) =
(hold time of flip-flop data pin)
+ (max clock delay from chip pin to FF pin)
- (min data delay from chip pin to FF pin)

calculating setup and holdtime

thanks sowmy. The links are awesome

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