*CMOS inverter
.PARAM V_SUPPLY = 3.3
.PARAM V_OUT = 2
*.PARAM INP_FREQ = '#INP_FREQ#'
*.PARAM INP_PERIOD = '1/INP_FREQ'
*.PARAM NO_PERIODS = '4'
*.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
*.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
.PARAM AC_POINTS = 10
.PARAM AC_START = 1000
.PARAM AC_STOP = 1E6
*** *** SUPPLY VOLTAGES *** ***
VDD VDD 0 'V_SUPPLY'
VSS VSS 0 0
*** *** INPUT SIGNAL *** ***
VSIG IN VSS AC 1 DC 1
*** *** CIRCUIT UNDER TEST *** ***
MP OUT IN VDD VDD P1 W=0.07963 L=0.001
MN OUT IN VSS VSS N1 W=0.03982 L=0.001
** CL OUT VSS 3p
RIN IN VSS 1G
Rf OUT IN 0.01
** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292
*** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** ***
*VOUT VOUT 0 'V_OUT'
IOUT OUT VSS AC 1 DC 1
*** *** ANALYSIS *** ***
*.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
*.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
*
*.PROBE TRAN V(IN)
*.PROBE TRAN V(OUT)
.OPTION POST PROBE ACCURATE
.include modelcard.nmos
.include modelcard.pmos
.control
*AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
AC dec 10 1000 1E6
let ROUT=OUT/(i(Vss))
plot ROUT
print ROUT > ROUT.log
.endc
.END
let ROUT=OUT/(i(OUT))
two AC sources activated simultaneously, VSIG and IOUT.
*CMOS inverter
.PARAM V_SUPPLY = 3.3
.PARAM V_OUT = 2
*.PARAM INP_FREQ = '#INP_FREQ#'
*.PARAM INP_PERIOD = '1/INP_FREQ'
*.PARAM NO_PERIODS = '4'
*.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
*.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
.PARAM AC_POINTS = 10
.PARAM AC_START = 1000
.PARAM AC_STOP = 1E6
*** *** SUPPLY VOLTAGES *** ***
VDD VDD 0 'V_SUPPLY'
VSS VSS 0 0
*** *** INPUT SIGNAL *** ***
VSIG IN VSS 0
*** *** CIRCUIT UNDER TEST *** ***
MP OUT IN VDD VDD P1 W=0.07963 L=0.001
MN OUT IN VSS VSS N1 W=0.03982 L=0.001
** CL OUT VSS 3p
RIN IN VSS 1G
Rf OUT IN 0.01
** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292
*** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** ***
*VOUT VOUT 0 'V_OUT'
IOUT OUT VSS AC 1 DC 1
*** *** ANALYSIS *** ***
*.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
*.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
*
*.PROBE TRAN V(IN)
*.PROBE TRAN V(OUT)
.OPTION POST PROBE ACCURATE
.include modelcard.nmos
.include modelcard.pmos
.control
*AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
AC dec 10 1000 1E6
let ROUT=OUT/(i(VSS))
plot ROUT
print ROUT > ROUT.log
.endc
.END
you want DC bias but no AC source.
*CMOS inverter
.PARAM V_SUPPLY = 3.3
.PARAM V_OUT = 2
*.PARAM INP_FREQ = '#INP_FREQ#'
*.PARAM INP_PERIOD = '1/INP_FREQ'
*.PARAM NO_PERIODS = '4'
*.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
*.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
.PARAM AC_POINTS = 10
.PARAM AC_START = 1000
.PARAM AC_STOP = 1E6
*** *** SUPPLY VOLTAGES *** ***
VDD VDD 0 'V_SUPPLY'
VSS VSS 0 0
*** *** INPUT SIGNAL *** *** set Vgs manually such that both mosfets are at saturation
VSIG IN VSS AC 1 DC 'V_SUPPLY/2'
*** *** CIRCUIT UNDER TEST *** ***
MP OUT IN VDD VDD P1 W=2U L=2U
MN OUT IN VSS VSS N1 W=1U L=2U
** CL OUT VSS 3p
** RIN IN VSS 1G
** CIN IN VSS 111
** Rf OUT IN 0.01
** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292
*** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** ***
*VOUT VOUT 0 'V_OUT'
*** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS
IOUT VSS OUT AC 1
*** *** ANALYSIS *** ***
*.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
*.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
*
*.PROBE TRAN V(IN)
*.PROBE TRAN V(OUT)
.OPTION POST PROBE ACCURATE
.include modelcard.nmos
.include modelcard.pmos
.control
*AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
AC dec 10 1000 1E6
let ROUT=OUT/abs(i(VSS))
plot ROUT
print ROUT > ROUT.log
.endc
.END
Don't agree. It makes particularly sense if you want to guarantee that the circuit is biased in active range (both transistors in saturation) without tuning a DC voltage.The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source
VSIG IN VSS [COLOR="#FF0000"]AC 1[/COLOR] DC 'V_SUPPLY/2'
You must not place a second AC source along with the bias circuit.
*CMOS inverter
.PARAM V_SUPPLY = 3.3
.PARAM V_OUT = 2
*.PARAM INP_FREQ = '#INP_FREQ#'
*.PARAM INP_PERIOD = '1/INP_FREQ'
*.PARAM NO_PERIODS = '4'
*.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
*.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
.PARAM AC_POINTS = 10
.PARAM AC_START = 1000
.PARAM AC_STOP = 1E6
*** *** SUPPLY VOLTAGES *** ***
VDD VDD 0 'V_SUPPLY'
VSS VSS 0 0
*** *** INPUT SIGNAL *** ***
VSIG IN VSS 0
** VSIG IN VSS AC 1 DC 'V_SUPPLY/2'
*** *** CIRCUIT UNDER TEST *** ***
MP OUT IN VDD VDD P1 W=2U L=2U
MN OUT IN VSS VSS N1 W=1U L=2U
** CL OUT VSS 3p
** RIN IN VSS 1G
CIN IN VSS 1E9
Rf OUT IN 1E9
** Lf OUT IN 1E-12
** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292
*** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** ***
*VOUT VOUT 0 'V_OUT'
*** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS
IOUT VSS OUT AC 1
*** *** ANALYSIS *** ***
*.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
*.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
*
*.PROBE TRAN V(IN)
*.PROBE TRAN V(OUT)
.OPTION POST PROBE ACCURATE
.include modelcard.nmos
.include modelcard.pmos
.control
*AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
AC dec 10 1000 1E6
let ROUT=OUT/abs(i(VSS))
plot ROUT
print ROUT > ROUT.log
.endc
.END
*CMOS inverter https://electronics.stackexchange.com/questions/383552/measurement-of-output-impedance-of-a-cmos-inverter
.PARAM V_SUPPLY = 3.3
.PARAM V_OUT = 2
*.PARAM INP_FREQ = '#INP_FREQ#'
*.PARAM INP_PERIOD = '1/INP_FREQ'
*.PARAM NO_PERIODS = '4'
*.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
*.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
.PARAM AC_POINTS = 10
.PARAM AC_START = 1000
.PARAM AC_STOP = 1E6
*** *** SUPPLY VOLTAGES *** ***
VDD VDD 0 'V_SUPPLY'
VSS VSS 0 0
*** *** INPUT SIGNAL *** ***
** VSIG IN VSS 0
** VSIG IN VSS AC 1 DC 0
** VSIG IN VSS AC 1 DC 'V_SUPPLY/2'
*** *** CIRCUIT UNDER TEST *** ***
MP OUT IN VDD VDD P1 W=2U L=2U
MN OUT IN VSS VSS N1 W=1U L=2U
** CL OUT VSS 3p
** RIN IN VSS 1G
CIN IN VSS 1
Rf OUT IN 1E15
** Lf OUT IN 1E-15
** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292
*** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT AND VARIABLE TEST VOLTAGE (VOUT) *** ***
*VOUT VOUT 0 'V_OUT'
*** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS
IOUT VSS OUT AC 1
*** *** ANALYSIS *** ***
*.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
*.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
*
*.PROBE TRAN V(IN)
*.PROBE TRAN V(OUT)
.OPTION POST PROBE ACCURATE
.include modelcard.nmos
.include modelcard.pmos
.control
*AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
AC dec 10 1000 1E6
let ROUT=OUT/abs(i(VSS))
plot ROUT
print ROUT > ROUT.log
.endc
.END
Code VHDL - [expand] 1 IOUT VSS OUT AC 1
Code VHDL - [expand] 1 let ROUT=V(OUT)
*CMOS inverter https://electronics.stackexchange.com/questions/383552/measurement-of-output-impedance-of-a-cmos-inverter
.PARAM V_SUPPLY = 3.3
.PARAM V_OUT = 2
*.PARAM INP_FREQ = '#INP_FREQ#'
*.PARAM INP_PERIOD = '1/INP_FREQ'
*.PARAM NO_PERIODS = '4'
*.PARAM TMEAS_START = '(NO_PERIODS-1)*INP_PERIOD'
*.PARAM TMEAS_STOP = '(NO_PERIODS)*INP_PERIOD'
.PARAM AC_POINTS = 10
.PARAM AC_START = 1000
.PARAM AC_STOP = 1E6
*** *** SUPPLY VOLTAGES *** ***
VDD VDD 0 'V_SUPPLY'
VSS VSS 0 0
*** *** INPUT SIGNAL *** ***
** VSIG IN VSS 0
** VSIG IN VSS AC 1 DC 0
** VSIG IN VSS AC 1 DC 'V_SUPPLY/2'
*** *** CIRCUIT UNDER TEST *** ***
MP OUT IN VDD VDD P1 W=2U L=2U
MN OUT IN VSS VSS N1 W=1U L=2U
** CL OUT VSS 3p
** RIN IN VSS 1G
CIN IN VSS 1
Rf OUT IN 1E15
** Lf OUT IN 1E-15
** The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source, see https://www.edaboard.com/showthread.php?377214-Noise-in-CMOS-Inverter&p=1617292&viewfull=1#post1617292
*** *** ROUT TEST SIGNAL WITH FIXED 1A CURRENT *** ***
** this is a way to measure or plot the current source IOUT in spice using 0V voltage source
VOUT OUT VOUT 0
*** *** IOUT flows into the output of the circuit under test, so negative terminal node of this current source is OUT instead of VSS
IOUT VSS VOUT AC 1
*** *** ANALYSIS *** ***
*.AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
*.TRAN 'INP_PERIOD/1000' 'NO_PERIODS*INP_PERIOD'
*
*.PROBE TRAN V(IN)
*.PROBE TRAN V(OUT)
.OPTION POST PROBE ACCURATE
.include modelcard.nmos
.include modelcard.pmos
** https://github.com/imr/ngspice/blob/master/examples/xspice/table/modelcards/modelcard.nmos
** https://github.com/imr/ngspice/blob/master/examples/xspice/table/modelcards/modelcard.pmos
.control
*AC dec 'AC_POINTS' 'AC_START' 'AC_STOP'
AC dec 10 1000 1E6
let ROUT=v(OUT)/abs(i(VOUT))
plot ROUT
print ROUT > ROUT.log
.endc
.END
Rf may be a way too high if the MOSFETs show leakage current.
Check the bias point!
... generates a (nearly) full feedback amplifier, i.e. gain≈1 for low frequencies (LF), with corresponding low LF output impedance. Did you consider this?... using your advice give me lower output impedance, about 8 kilo ohms lower compared to theoretical calculation.
Code VHDL - [expand] 1 Rf OUT IN 1E15
Not in the frequency range of interest with 1F filter capacitor!... generates a (nearly) full feedback amplifier, i.e. gain≈1 for low frequencies (LF), with corresponding low LF output impedance.
You didn't tell before how much the expected value is. 20% deviation sounds realistic.Why if I decrease Rf from 1E15 to 1E9 , ROUT increases from 48.563 kohm to 48.5705 kohm
Means check the bias resistor voltage drop. Apparently it's acceptable. That's it.This is a self-bias CMOS inverter. Could you advise ?
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