Problem in Virtuoso cadence...

[cipher_crypto]

virtuoso verilog example

Hi,
I was designing a FFT processor with verilog. When I was using virtuoso tool I faced problem. My code worked well in Xilinx.
FFT1 << top module
butterfly3 is instance of another module radix1. Now I am getting error message like this "Error: Netlister unable to descend any of the views defined in the view list "verilog schematic extracted" for instance butterfly 3 in cell FFT1. Either one of these views to library FFT1_lib cell: radix1 modify the view list to ....an existing view"
I already listed this radix1 in my system....
Please let me know how to solve this problem...

cipher

 

[delei]

virtuoso verilog-xl environment

You need check the view name of radix1 cell.The netlister don't find the view name
verilog or schematic or extracted in radix1 cell,so netlister can't generate netlist.

 

[cipher_crypto]

virtuoso verilog environment

Hi Delei,
Thank you. I just started this tool. I basically following this followin instruction to use virtuoso. In this tutorial it shows to run example BCDcounter << I am following these instructions to run my program ::

Verilog-Editor Editing window:
Tools -> Verilog-XL


Setup Environment window:
Run Directory = BCDcounter.run1
OK


Virtuoso Verilog Environment for Verilog-XL Integration window:
Setup -> Record Signals


Record Signals Options window:
Choose to save "All Signals"
Waveform Display Package -> Simvision
OK


Virtuoso Verilog Environment for Verilog-XL Integration window:
Stimulus -> Verilog


New window:
Click Yes to create stimulus template file
<<<< I got the ERROR message after this step

I basically listed RADIX1 in the list. I dont know why netlister is not viewing it. Could you tell me I am following the right steps? Do u have any other reference I can follow?
Please let me know.