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Problem in VCS Simulation with UPF

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hayoula

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Hi,
I am using VCS with UPF support to simulate my circuit with power intent.
At the start of simulation it gives me this message:

MV_PERF_INIT_STATE: design has started with state illegal_state in pst testbench/spdaa0/pw_st_tbl

I have defined all possible states in power state table "pw_st_tbl", but it does not work properly.
Can anyone help?
 

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