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Problem in Utilization Area

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Bustigo

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my Utilization is about 80 % not maped although the slices not mapped are reported to be not large ( = 1% of remaide area)
i have ths question
If i have an entity consists of many components
how can i know utilization of each without making each compoenent as a top level
in ISE xilinx
 

compile the lot.
The compilation reports should show the area breakdown by entity.
 

You can compile with "hierarchy" on or soft.
Then, open up Floorplanner or PlanAhead. You can see how much resource each component takes.

In my opinion, 80% is too high. (But, I know other engineers who feel comfortable with even higher than 80%). I was burned by unroutable design with very high utilization number.... Just my opinion. :)
 

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