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| Synopsys Unified Verilog-A (pVA v3.0) |
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| Machine Name: DESKTOP-FNK1C3V |
| Copyright (c) 2013 Synopsys Inc., All Rights Reserved. |
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libepva built by hspmgr synmake_pva_build on Wed Jul 24 10:18:53 CST 2013
HSP_HOME: C:\synopsys\Hspice_H-2013.03-SP2
HSP_ARCH: win64
HSP_GCC : C:\synopsys\Hspice_H-2013.03-SP2\GNU\win64\bin\gcc
HSP_GCC_VER: 3.4.5
Working-Dir: C:\Users\safir rayaneh\Desktop\veriloga-hspice
Args: -p hsp -t spi -f resistor.pvadir/pvaHDL.lis -o resistor.pvadir
### optimize mode ###
Args: pva -p hsp -t spi -f resistor.pvadir/pvaHDL.lis -o resistor.pvadir
Begin of pVA compiling on Fri Dec 07 11:31:02 2018
Parsing './resistor.va'
Parsing include file 'C:/synopsys/Hspice_H-2013.03-SP2/include/disciplines.vams'
End of pVA compiling on Fri Dec 07 11:31:02 2018
End of build pVA DB on Fri Dec 07 11:31:02 2018
*pvaI* Module (resistor): 2 unexpanded port, 0 init, 1 behav, 1 contrib, 11/0 expr(s)
*pvaI* No DIS, 0 afCount, 0 MT
*pvaI* 1 const-G and 0 const-C, No switchBranch, 0 bypassOpt
*pvaI* generated 0 flow node(s) during compilation.
End of pVA genC on Fri Dec 07 11:31:05 2018
*pvaI* #### Total 99 line-size(s), 11/0 expr(s), 1 contr(s), 0 init(s), 1 behav(s), 2 port(s)
Generating resistor.pvadir\pvaRTL_win64.dll
pVA concluded on Fri Dec 07 11:31:29 2018