Jan 29, 2016 #1 A Ahmed Hisham Newbie level 3 Joined Nov 11, 2014 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 27 Code: module aaa(input logic a,b,c,output logic y); assign y=~a&~b&~c | a&~b&~c | a&~b&c; endmodule i am using Quartus for simultion at the begining of the creation of the project i chosed verilog as there is no for system verilog now this error is given to me for the code a Error (10161): Verilog HDL error at aaa.v(2): object "logic" is not declared
Code: module aaa(input logic a,b,c,output logic y); assign y=~a&~b&~c | a&~b&~c | a&~b&c; endmodule i am using Quartus for simultion at the begining of the creation of the project i chosed verilog as there is no for system verilog now this error is given to me for the code a Error (10161): Verilog HDL error at aaa.v(2): object "logic" is not declared
Jan 29, 2016 #2 dpaul Advanced Member level 5 Joined Jan 16, 2008 Messages 1,799 Helped 317 Reputation 635 Reaction score 342 Trophy points 1,373 Location Germany Activity points 13,073 You have two options: 1> Use a compiler and simulator that supports System Verilog constructs. 2> If not<1>, then change your 'module aaa' to Verilog Converting it to Verilog or for the matter of fact writing a new Verilog module seems pretty easy from the logic you have provided. That is your task! So this SV cheatsheet might help you in case you want to go with option <2>. https://www.cl.cam.ac.uk/teaching/1112/ECAD+Arch/files/SystemVerilogCheatSheet.pdf
You have two options: 1> Use a compiler and simulator that supports System Verilog constructs. 2> If not<1>, then change your 'module aaa' to Verilog Converting it to Verilog or for the matter of fact writing a new Verilog module seems pretty easy from the logic you have provided. That is your task! So this SV cheatsheet might help you in case you want to go with option <2>. https://www.cl.cam.ac.uk/teaching/1112/ECAD+Arch/files/SystemVerilogCheatSheet.pdf
Jan 29, 2016 #3 A Ahmed Hisham Newbie level 3 Joined Nov 11, 2014 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 27 does the later versions of Quartus support system verilog
Jan 29, 2016 #4 ads-ee Super Moderator Staff member Joined Sep 10, 2013 Messages 7,944 Helped 1,822 Reputation 3,654 Reaction score 1,808 Trophy points 1,393 Location USA Activity points 60,207 Try using the file extension .sv instead. If Quartus simulator is anything like Vivado's it will automatically use system verilog if it sees yhat extension.
Try using the file extension .sv instead. If Quartus simulator is anything like Vivado's it will automatically use system verilog if it sees yhat extension.