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problem in signaltap Quartus II

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Full Member level 2
Feb 22, 2012
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Hello friends,

I'm a newbe in signaltap tool in Quartus II. I can configure the signaltap to see input/output pins changes.
But when I want to see the changes of registers of my design, it just shows '0' value without change and also one warning is added to the critical warnings:

Critical Warning: Partially connected in-system debug instance "auto_signaltap_0" to 1 of its 27 required data inputs, trigger inputs, acquisition clocks, and dynamic pins. There were 0 illegal, 0 inaccessible, and 26 missing sources or connections.

would you please help me?

Thanks in advance.

Apparently ou didn't tap the registers in the right place, or the registers have been discarded during synthesis because they are functionless in your design.

Presumed the registers actually exist, it can be best accessed in the module that sources the signal.

In fact, I have the same problem for all the registers.

Yes, may be. Hard to understand without knowing the design.

The problem was related to the register.
I mean my defined register wasn't doing anything in my design, so quartus had removed it from register groups and had counted the register as a combinational signal.

use synthesis=keep synthesis=perserve in your code to make sure Quartus doesn't strip out the registers.

You'll have to check whether or not you need both or just one of the statements as I've had mixed results using them with various versions of the tools. Sometimes there are weird bugs that require you to use only one of them or both of them together. I've always ended up having to experiment. :-?
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