problem in register interfacing

[gmish27]

here is my code that i have used to make a register for my basic computer:

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Code Verilog - [expand]
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module register #(parameter n=2)
    (
    input inc,we,
    input clr,clk,
    input [n-1:0] idat,
    output [n-1:0] odat
    );
     
    reg [n-1:0] data;
    
    always@(posedge clk, posedge clr)
        if(clr)
            data <= 0;
        else if(inc)
            data <= data + 1;
        else if(we)
            data <= idat;
            
    assign odat = data;
 
 
endmodule

---

Now when i am using this register as a top module to check the functioning of it like if provide an 'inc=1'b1' signal in the test bench, the output i.e 'odat' becomes high in the same clock cycle.

But when i interface this register to the control signals as if:
inc = control_signal[1];

the output 'odat' gets high in the next clock cycle. please tell why???

 

[dftrtl]

For first case you need to see the relation of inc=1'b1 wrt clk in your test bench
Make inc=1'b1 wrt @clk then you should not see a problem