problem in receiving from gsm modem interface with microcontroller

Similar threads

• X

  Still have problem with understanding `include in Verilog

  • Started by Xenon02
  • Oct 2, 2023
  • Replies: 8

  PLD, SPLD, GAL, CPLD, FPGA Design
• R

  problem of fpga

  • Started by rllv24
  • Mar 24, 2024
  • Replies: 3

  PLD, SPLD, GAL, CPLD, FPGA Design
• Have a timing problem with source synchronous DDR interface

  • Started by ILIA KALISTRU
  • Oct 8, 2022
  • Replies: 0

  PLD, SPLD, GAL, CPLD, FPGA Design
• M

  Problem with PS/2 communication over UART

  • Started by mtaciano
  • Jul 7, 2023
  • Replies: 5

  PLD, SPLD, GAL, CPLD, FPGA Design
• A

  Use interface signals as inout in systemverilog

  • Started by antlhem
  • Apr 1, 2023
  • Replies: 0

  PLD, SPLD, GAL, CPLD, FPGA Design